VLSI implementation of the motion estimator with two-dimensional data-reuse

Yeong Kang Lai, Yeong Lin Lai, Yuan Chen Liu, Liang Gee Chen

研究成果: Article

5 引文 斯高帕斯(Scopus)

摘要

This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

原文English
頁(從 - 到)623-629
頁數7
期刊IEEE Transactions on Consumer Electronics
44
發行號3
DOIs
出版狀態Published - 1998 十二月 1

    指紋

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Electrical and Electronic Engineering

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