The novel Chinese abacus adder

Zi Yi Zhao, Chien Hung Lin, Yu Zhi Xie, Yen Ju Chen, Yi Jie Lin, Shu Chung Yi

研究成果: Conference contribution

8 引文 斯高帕斯(Scopus)

摘要

A novel Chinese abacus adder is presented in this paper. The simulation results of 8-bit adders are compared with those of CLA (Carry Look-ahead) adder and RCA (Ripple carry adder) by all input patterns. The delay of the 8-bit abacus adder is 22%, and 14% less than those of CLA adders for 0.35μm and 0.18μm technologies, respectively. The power consumption of the abacus adders are 30% and 60% less than those of CLA adders for 0.35μm, and 0.18μm technologies, respectively. The delay of the 32-bit abacus adder is 17%, and 12% less than those of CLA adder for 0.35μm, and 0.18μm technologies, respectively.

原文English
主出版物標題2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs
出版狀態Published - 2007 九月 28
事件2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan
持續時間: 2007 四月 252007 四月 27

出版系列

名字2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Other

Other2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
國家Taiwan
城市Hsinchu
期間07-04-2507-04-27

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • 引用此

    Zhao, Z. Y., Lin, C. H., Xie, Y. Z., Chen, Y. J., Lin, Y. J., & Yi, S. C. (2007). The novel Chinese abacus adder. 於 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers [4239453] (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2007.372759