Spatial scanning-probe array system for silicon-on-insulator integrated circuits

研究成果: Conference contribution

摘要

A spatial scanning-probe array system for silicon-on-insulator (SOI) integrated circuit is proposed in this paper. The operating fundamentals, specifications, and simulations are presented in this paper. The proposed system is designed to scan the circuit in order to examine the surface and detect die cracks. The post signal processing by using discrete wavelet transform (DWT) for scattered optical signal is also proposed and simulated.

原文English
主出版物標題2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
頁面910-913
頁數4
DOIs
出版狀態Published - 2008 十月 27
事件2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS - Knoxville, TN, United States
持續時間: 2008 八月 102008 八月 13

出版系列

名字Midwest Symposium on Circuits and Systems
ISSN(列印)1548-3746

Other

Other2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
國家United States
城市Knoxville, TN
期間08-08-1008-08-13

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • 引用此

    Yang, W. R. (2008). Spatial scanning-probe array system for silicon-on-insulator integrated circuits. 於 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS (頁 910-913). [4616948] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2008.4616948