Self-Checking Residue Number System for Low-Power Reliable Neural Network

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

Neural Network suffers four major issues including acceleration, power consumption, area overhead and fault tolerance. In this paper we develop a systematic approach to design a low-power, compact, fast and reliable neural network based on a redundant residue number system. Residue number systems have been applied in designing neural network except the CORDIC-based activation functions including hypertangent, logistic and softmax functions. This issue results in that the entire neural network cannot be totally self-checked and extra operations make the time, power and area reductions wasted. In our systematic approach we propose some design rules for ensuring the checking rate without loss of reductions in time, area and power consumption. From experiments on three neu-ral network with 24-bit fixed-point operations for the MNIST handwritten digit data set, 3, 4, and 5 moduli are separately employed for achieving all balanced improvements in power-saving, area-reduction, speed-acceleration and reliability pro-motion. Experimental results show that all the power, time and area can be reduced to only about one third, and the entire network in any combination of software and hardware can be self-checked in an aliasing rate of only 0.39% and TMR-correctable under the single-residue fault model.

原文English
主出版物標題Proceedings - 2019 IEEE 28th Asian Test Symposium, ATS 2019
發行者IEEE Computer Society
頁面37-42
頁數6
ISBN(電子)9781728126951
DOIs
出版狀態Published - 2019 十二月
事件28th IEEE Asian Test Symposium, ATS 2019 - Kolkata, India
持續時間: 2019 十二月 102019 十二月 13

出版系列

名字Proceedings of the Asian Test Symposium
2019-December
ISSN(列印)1081-7735

Conference

Conference28th IEEE Asian Test Symposium, ATS 2019
國家India
城市Kolkata
期間19-12-1019-12-13

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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