Low test-application time method for EEPLA testing

K. C. Wei, B. D. Liu, J. J. Tang

研究成果: Article同行評審

摘要

An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected.

原文English
頁(從 - 到)39-42
頁數4
期刊IEE Proceedings: Computers and Digital Techniques
144
發行號1
DOIs
出版狀態Published - 1997 一月 1

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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