IR drop reduction via a flip-flop resynthesis technique

Jiun Kuan Wu, Tsung Yi Wu, Liang Ying Lu, Kuang Yao Chen

研究成果: Conference contribution

6 引文 斯高帕斯(Scopus)

摘要

Clock skew scheduling for peak current reduction is a conventional technique for solving IR-drop problem in physical design stage. In this paper, we propose two kinds of long delay flip-flops and a heuristic algorithm that is used to resynthesize flip-flops of a circuit. Because the switching times of flip-flops in the resynthesized circuit are staggered, the IR drop effect can be reduced. Unlike clock skew scheduling, our technique not only can be used in physical design stage but also in logic design stage. The other advantages of our technique over the clock skew optimization technique are that our technique has less area overhead and has more opportunities to find a better result.

原文English
主出版物標題Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008
頁面78-83
頁數6
DOIs
出版狀態Published - 2008 八月 25
事件9th International Symposium on Quality Electronic Design, ISQED 2008 - San Jose, CA, United States
持續時間: 2008 三月 172008 三月 19

出版系列

名字Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Other

Other9th International Symposium on Quality Electronic Design, ISQED 2008
國家United States
城市San Jose, CA
期間08-03-1708-03-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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