This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application. The basic idea is to identify an input control pattern for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be minimized or even eliminated. A D-algorithm-like pattern generator is developed to generate the control pattern. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve about 19.29% of average improvement, while 29.28% average improvement can be achieved if the input control technique is employed before the vector ordering and the latch ordering techniques.
|頁（從 - 到）||315-320|
|期刊||Proceedings of the Asian Test Symposium|
|出版狀態||Published - 1999 十二月 1|
|事件||Proceedings of the 1999 8th Asian Test Symposium (ATS'99) - Shanghai, China|
持續時間: 1999 十一月 16 → 1999 十一月 18
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering