In this paper we propose a power amplifier (PA) for high output power and high linearity WCDMA applications. This PA is designed based on a three-stage configuration and an output stage designed by a multiple gated transistor topology. The test chip is simulated and fabricated with the TSMC 0.18μm CMOS process. Simulation results show that the power amplifier achieves 24.4 dB of power gain, 25 dBm of 1dB compression power output, and 27.6 dBm at third order output interception point (OIP3). The power added efficiency (PAE) at gain compression point is 33.5%. The die size is 1.2 × 1.2 mm2.