High power CMOS power amplifier for WCDMA

Yu Chun Huang, Zhi-Ming Lin

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

In this paper we propose a power amplifier (PA) for high output power and high linearity WCDMA applications. This PA is designed based on a three-stage configuration and an output stage designed by a multiple gated transistor topology. The test chip is simulated and fabricated with the TSMC 0.18μm CMOS process. Simulation results show that the power amplifier achieves 24.4 dB of power gain, 25 dBm of 1dB compression power output, and 27.6 dBm at third order output interception point (OIP3). The power added efficiency (PAE) at gain compression point is 33.5%. The die size is 1.2 × 1.2 mm2.

原文English
主出版物標題APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
頁面199-202
頁數4
DOIs
出版狀態Published - 2006 十二月 1
事件APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
持續時間: 2006 十二月 42006 十二月 6

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
國家Singapore
期間06-12-0406-12-06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • 引用此

    Huang, Y. C., & Lin, Z-M. (2006). High power CMOS power amplifier for WCDMA. 於 APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (頁 199-202). [4145365] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342366