Hardware accelerator for boosting convolution computation in image classification applications

Meng Chou Chang, Ze Gang Pan, Jyun Liang Chen

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).

原文English
主出版物標題2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509040452
DOIs
出版狀態Published - 2017 十二月 19
事件6th IEEE Global Conference on Consumer Electronics, GCCE 2017 - Nagoya, Japan
持續時間: 2017 十月 242017 十月 27

出版系列

名字2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017
2017-January

Other

Other6th IEEE Global Conference on Consumer Electronics, GCCE 2017
國家Japan
城市Nagoya
期間17-10-2417-10-27

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Instrumentation
  • Electrical and Electronic Engineering

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    Chang, M. C., Pan, Z. G., & Chen, J. L. (2017). Hardware accelerator for boosting convolution computation in image classification applications. 於 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 (2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017; 卷 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/GCCE.2017.8229395