Exploiting instruction-level parallelism with the conjugate register file scheme

Meng chou Chang, Feipei Lai, Rung ji Shang

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper proposes a new micro-architecture, called IAS-S, which takes advantage of the Conjugate Register File (CRF) scheme to support speculative execution, such as multi-level boosting and multi-way branch, without incurring excessive hardware overhead. A software technique which integrates register allocation and instruction scheduling has been developed to exploit the conjugate register file. The scheduling-conflict graph is built before the starting of register allocation so that the ability of the instruction scheduler to optimize the instruction sequence will not be severely restricted by the reuse of registers.

原文English
主出版物標題Proceedings of the 25th Annual International Symposium on Microarchitecture
發行者Publ by ACM
頁面29-32
頁數4
ISBN(列印)0818631759, 9780818631757
DOIs
出版狀態Published - 1992
事件Proceedings of the 25th Annual International Symposium on Microarchitecture - Portland, OR, USA
持續時間: 1992 十二月 11992 十二月 4

出版系列

名字Proceedings of the 25th Annual International Symposium on Microarchitecture

Other

OtherProceedings of the 25th Annual International Symposium on Microarchitecture
城市Portland, OR, USA
期間92-12-0192-12-04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • 引用此

    Chang, M. C., Lai, F., & Shang, R. J. (1992). Exploiting instruction-level parallelism with the conjugate register file scheme. 於 Proceedings of the 25th Annual International Symposium on Microarchitecture (頁 29-32). (Proceedings of the 25th Annual International Symposium on Microarchitecture). Publ by ACM. https://doi.org/10.1145/144965.144986