Design of delay-locked loop for wide frequency locking range

Hsun-Hsiang Chen, Zih Hsiang Wong, Shen Li Chen

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

In order to increase the frequency locking range, a delay-locked loop (DLL) circuit with frequency to voltage converter (FVC) and phase select circuit is described. For the low power dissipation consideration, the circuit's bias current is keep at lower level. The simulation results show that the operating frequency range extend from 106 MHz ∼ 151 MHz to 54 MHz ∼ 250 MHz, and the power dissipation increases from 2.47 mW ∼ 3.33 mW to 6.7 mW ∼ 14 mW.

原文English
主出版物標題ISOCC 2013 - 2013 International SoC Design Conference
發行者IEEE Computer Society
頁面302-305
頁數4
ISBN(列印)9781479911417
DOIs
出版狀態Published - 2013 一月 1
事件2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
持續時間: 2013 十一月 172013 十一月 19

Other

Other2013 International SoC Design Conference, ISOCC 2013
國家Korea, Republic of
城市Busan
期間13-11-1713-11-19

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Chen, H-H., Wong, Z. H., & Chen, S. L. (2013). Design of delay-locked loop for wide frequency locking range. 於 ISOCC 2013 - 2013 International SoC Design Conference (頁 302-305). [6864033] IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6864033