Design of an asynchronous pipelined processor

Meng-Chou Chang, Da Sen Shiau

研究成果: Conference contribution

6 引文 斯高帕斯(Scopus)

摘要

Asynchronous circuits have the potential advantages of low power consumption, high operating speed, low electromagnetic emission, no clock skew problem, and robustness towards variations in temperature, supply voltage and fabrication process parameters. This paper introduces the design of an asynchronous pipelined processor, called AsynRISC, which is implemented by using the asynchronous hardware description language Balsa. Since asynchronous logic adopts distributed control scheme, the traditional methods for handling hazards in synchronous processors can not be directly applied to asynchronous processors. In this paper, the methods for dealing with data hazards and control hazards in AsynRISC are discussed.

原文English
主出版物標題2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
頁面1093-1096
頁數4
DOIs
出版狀態Published - 2008 十二月 1
事件2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province, China
持續時間: 2008 五月 252008 五月 27

出版系列

名字2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

Other

Other2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
國家China
城市Xiamen, Fujian Province
期間08-05-2508-05-27

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

指紋 深入研究「Design of an asynchronous pipelined processor」主題。共同形成了獨特的指紋。

引用此