Comparative design of floating-point arithmetic units using the Balsa synthesis system

Ren-Der Chen, Yu Cheng Chou, Wan Chen Liu

研究成果: Conference contribution

摘要

In this paper, the asynchronous floating-point arithmetic units consisting of adders/subtractors and multipliers are designed and compared based on the Balsa synthesis system. For the critical mantissa multiplication in the multiplier, the modified Booth algorithm (radix 2, 4, and 8) is adopted. A pipelined design of the multiplier is also presented to increase performance. Since the Balsa language is compiled using syntax-directed translation, for the two different if statements and one case statement supported by Balsa, three different description styles have been made for each design. It can be seen from the experimental results how the style affects the area cost and simulation time of the resulting circuit. This gives us a guide to choose appropriate control statements for designing Balsa-based asynchronous circuits.

原文English
主出版物標題2011 International Symposium on Integrated Circuits, ISIC 2011
頁面172-175
頁數4
DOIs
出版狀態Published - 2011 十二月 1
事件2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, Singapore
持續時間: 2011 十二月 122011 十二月 14

出版系列

名字2011 International Symposium on Integrated Circuits, ISIC 2011

Other

Other2011 International Symposium on Integrated Circuits, ISIC 2011
國家Singapore
城市SingaporeSingapore
期間11-12-1211-12-14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • 引用此

    Chen, R-D., Chou, Y. C., & Liu, W. C. (2011). Comparative design of floating-point arithmetic units using the Balsa synthesis system. 於 2011 International Symposium on Integrated Circuits, ISIC 2011 (頁 172-175). [6131905] (2011 International Symposium on Integrated Circuits, ISIC 2011). https://doi.org/10.1109/ISICir.2011.6131905