This paper applied the Taguchi method to simulate the latch-up effect of nLDMOS to achieve an optimization design. The applied model is for an nLDMOS structure with high voltage well plus the adaptive (adjustment) layers of source & drain, and an N-type buried layer. Although the methods we could choose is abundant, we hope to effectively obtain the data which is useful for statistics in order to judge the correct characteristic of parameters. We applied the Taguchi method to perform an optimization in the paper. There are six parameters with two levels in this work, so we choose the Taguchi table to be L 8(2 7). By this way, it can decrease the times of experiment much effectively.
|頁（從 - 到）||81-84|
|期刊||Advanced Materials Research|
|出版狀態||Published - 2012 四月 4|
|事件||3rd international Conference on Manufacturing Science and Engineering, ICMSE 2012 - Xiamen, China|
持續時間: 2012 三月 27 → 2012 三月 29
All Science Journal Classification (ASJC) codes