A10-GHz 0.88-mW low-phase-noise CMOS VCO

Jin Rong Syu, Zhi-Ming Lin

研究成果: Conference contribution

摘要

In this paper, a 1.2-V 10-GHz low-power low-noise VCO is designed and fabricated in a 0.18μm CMOS process. By using noise-reduction techniques associated with the current-reused structure, the VCO can achieve lower power consumption and phase noise. The simulated power consumption is 0.88-mW. The simulated phase noise is -114.8- dBc/Hz at 1-MHz offset frequencies. The attained FOM is - 191.

原文English
主出版物標題2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09
頁面1063-1066
頁數4
DOIs
出版狀態Published - 2009 十二月 1
事件2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09 - Cancun, Mexico
持續時間: 2009 八月 22009 八月 5

出版系列

名字Midwest Symposium on Circuits and Systems
ISSN(列印)1548-3746

Other

Other2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09
國家Mexico
城市Cancun
期間09-08-0209-08-05

    指紋

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此

Syu, J. R., & Lin, Z-M. (2009). A10-GHz 0.88-mW low-phase-noise CMOS VCO. 於 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09 (頁 1063-1066). [5235985] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2009.5235985