A token scan architecture for low power testing

Tsung-Chu Huang, Kuen Jong Lee

研究成果: Conference article同行評審

33 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel scan architecture for low-power testing, which employs the techniques of multiphase clocking, token ring, and clockgating. When the multiphase clocking technique is directly employed to a scan chain, inter-phase skews and large routing area will be the problems. We develop a token scan cell design to address these problems. To reduce the power dissipation due to the clock and scan-in data trees, we propose a novel clockgating technique that takes the advantage of the regularity and periodicity of the token scan chain. Combining the three techniques, the token scan architecture can efficiently reduce the data transitions in the scan circuits as well as the switching activity in both the clock and the scan-in data trees. From experiments, more than 95% of power reduction can be achieved for most circuits with long scan chains.

原文English
頁(從 - 到)660-669
頁數10
期刊IEEE International Test Conference (TC)
出版狀態Published - 2001 十二月 1
事件International Test Conference 2001 Proceedings - Baltimore, MD, United States
持續時間: 2001 十月 302001 十一月 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

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