A pipeline structure for high-speed step-by-step RS decoding

Tung Chou Chen, Che Ho Wei, Shyue Win Wei

研究成果: Letter

3 引文 (Scopus)

摘要

Based on a modified step-by-step decoding procedure, a high-speed pipelined Reed-Solomon decoder is presented. The decoder requires only the delay time of three 2-input XOR gates for decoding each coded symbol. The decoder can be operated in a bit rate of Gbits/sec order and thus suitable for the very high speed data transmission systems.

原文English
頁(從 - 到)847-849
頁數3
期刊IEICE Transactions on Communications
E86-B
發行號2
出版狀態Published - 2003 二月

指紋

Decoding
Pipelines
Data communication systems
Time delay

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

引用此文

Chen, Tung Chou ; Wei, Che Ho ; Wei, Shyue Win. / A pipeline structure for high-speed step-by-step RS decoding. 於: IEICE Transactions on Communications. 2003 ; 卷 E86-B, 編號 2. 頁 847-849.
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A pipeline structure for high-speed step-by-step RS decoding. / Chen, Tung Chou; Wei, Che Ho; Wei, Shyue Win.

於: IEICE Transactions on Communications, 卷 E86-B, 編號 2, 02.2003, p. 847-849.

研究成果: Letter

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AB - Based on a modified step-by-step decoding procedure, a high-speed pipelined Reed-Solomon decoder is presented. The decoder requires only the delay time of three 2-input XOR gates for decoding each coded symbol. The decoder can be operated in a bit rate of Gbits/sec order and thus suitable for the very high speed data transmission systems.

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