TY - GEN
T1 - A low voltage four-quadrant CMOS analogue multiplier
AU - Lin, Zhi-Ming
AU - Huang, C. H.
PY - 1999/1/1
Y1 - 1999/1/1
N2 - A four-quadrant CMOS analogue multiplier is presented. Experimental results show that the multiplier has a dynamic input range, exceeding 60% of the power supply voltage (±0.5 V), and the linearity error is less than 0.07% at the maximum input range. The simulated maximum power dissipation for the multiplier is 2.83 mW.
AB - A four-quadrant CMOS analogue multiplier is presented. Experimental results show that the multiplier has a dynamic input range, exceeding 60% of the power supply voltage (±0.5 V), and the linearity error is less than 0.07% at the maximum input range. The simulated maximum power dissipation for the multiplier is 2.83 mW.
UR - http://www.scopus.com/inward/record.url?scp=84940380956&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84940380956&partnerID=8YFLogxK
U2 - 10.1109/ICECS.1999.814415
DO - 10.1109/ICECS.1999.814415
M3 - Conference contribution
AN - SCOPUS:84940380956
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 1333
EP - 1335
BT - Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999
Y2 - 5 September 1999 through 8 September 1999
ER -