A low voltage four-quadrant CMOS analogue multiplier

Zhi-Ming Lin, C. H. Huang

研究成果: Conference contribution

摘要

A four-quadrant CMOS analogue multiplier is presented. Experimental results show that the multiplier has a dynamic input range, exceeding 60% of the power supply voltage (±0.5 V), and the linearity error is less than 0.07% at the maximum input range. The simulated maximum power dissipation for the multiplier is 2.83 mW.

原文English
主出版物標題Proceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1333-1335
頁數3
ISBN(電子)0780356829
DOIs
出版狀態Published - 1999 一月 1
事件6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 - Pafos, Cyprus
持續時間: 1999 九月 51999 九月 8

出版系列

名字Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
3

Other

Other6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999
國家Cyprus
城市Pafos
期間99-09-0599-09-08

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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