A loop partition technique for reducing cache bank conflict in multithreaded architecture

Chao-Chin Wu, C. Chen

研究成果: Article

2 引文 斯高帕斯(Scopus)

摘要

Parallel multithreaded architectures take advantage of the ability to execute more than one thread simultaneously on a single chip at low synchronisation and communication costs and high hardware resource utilisation. However, a high bandwidth cache, such as a multibank cache, is especially critical to serve memory accesses issued at the same time from different threads. To prevent bank conflicts of multibank cache from seriously degrading system performance, a loop partition method is proposed to reduce or even eliminate bank conflicts. The partition allows each thread access to certain bank modules and prevents any two from accessing the same bank module. The method neither slows down the clock rate nor increases the array subscript expression complexity. The performance gains of the bank-conflict-free loop partition approach are shown in simulation results.

原文English
頁(從 - 到)30-36
頁數7
期刊IEE Proceedings: Computers and Digital Techniques
143
發行號1
DOIs
出版狀態Published - 1996 一月 1

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

指紋 深入研究「A loop partition technique for reducing cache bank conflict in multithreaded architecture」主題。共同形成了獨特的指紋。

  • 引用此