A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC

Yi Cheng Chen, Jyun Syong Lai, Zhi Ming Lin

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-μm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/-0.23 LSB differential non-linearity error (DNL) and +0.24/-0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.

原文English
主出版物標題2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs
出版狀態Published - 2013 十二月 23
事件2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong
持續時間: 2013 六月 32013 六月 5

Other

Other2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
國家Hong Kong
城市Hong Kong
期間13-06-0313-06-05

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • 引用此

    Chen, Y. C., Lai, J. S., & Lin, Z. M. (2013). A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC. 於 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 [6628099] https://doi.org/10.1109/EDSSC.2013.6628099