In this paper a 6-bit Flash Analog-to-Digital converter (ADC) implemented in TSMC 0.18-μm CMOS process is presented. Different from the conventional Flash ADCs, the architecture of the proposed ADC is based on single-ended comparators with a sample-and-hold (S/H) circuit. Single-ended comparators are formed using only inverters and resistors. Therefore, our design can reduce a lot of transistor numbers and power consumption. The designed ADC consumes 0.425 mW at 1.5V power supply. The speed of this design is 2 GS/s. The simulated static differential non-linearity error (DNL) and integral non-linearity error (INL) are between 0.4/-0.29 LSB and 0.4/-0.39 LSB, respectively.
|出版狀態||Published - 2012 一月 1|
|事件||2012 International Workshop on Computer Science and Engineering, WCSE 2012 - Hong Kong, Hong Kong|
持續時間: 2012 八月 3 → 2012 八月 4
|Conference||2012 International Workshop on Computer Science and Engineering, WCSE 2012|
|期間||12-08-03 → 12-08-04|
All Science Journal Classification (ASJC) codes
- Computer Science(all)