A 6-bit 2GS/s low power flash ADC

Jyun Syong Lai, Zhi Ming Lin

研究成果: Paper

1 引文 斯高帕斯(Scopus)

摘要

In this paper a 6-bit Flash Analog-to-Digital converter (ADC) implemented in TSMC 0.18-μm CMOS process is presented. Different from the conventional Flash ADCs, the architecture of the proposed ADC is based on single-ended comparators with a sample-and-hold (S/H) circuit. Single-ended comparators are formed using only inverters and resistors. Therefore, our design can reduce a lot of transistor numbers and power consumption. The designed ADC consumes 0.425 mW at 1.5V power supply. The speed of this design is 2 GS/s. The simulated static differential non-linearity error (DNL) and integral non-linearity error (INL) are between 0.4/-0.29 LSB and 0.4/-0.39 LSB, respectively.

原文English
頁面369-371
頁數3
出版狀態Published - 2012 一月 1
事件2012 International Workshop on Computer Science and Engineering, WCSE 2012 - Hong Kong, Hong Kong
持續時間: 2012 八月 32012 八月 4

Conference

Conference2012 International Workshop on Computer Science and Engineering, WCSE 2012
國家Hong Kong
城市Hong Kong
期間12-08-0312-08-04

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Engineering(all)

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  • 引用此

    Lai, J. S., & Lin, Z. M. (2012). A 6-bit 2GS/s low power flash ADC. 369-371. 論文發表於 2012 International Workshop on Computer Science and Engineering, WCSE 2012, Hong Kong, Hong Kong.