A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology

研究成果: Article

6 引文 斯高帕斯(Scopus)

摘要

A 5.25 GHz low voltage, high linear and isolated mixer using TSMC 0.18 μm CMOS process for WLAN receiver was investigated. The paper presents a novel topology mixer that leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7.6 dB power conversion gain, 11.4 dB double side band noise figure, 3 dBm input third-order intercept point, and the total dc power consumption of this mixer including output buffers is 2.45 mW from a 1 V supply voltage. The current output buffer is about 2 mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 37.8, 54.8 and 38.2 dB, respectively.

原文English
頁(從 - 到)301-312
頁數12
期刊Analog Integrated Circuits and Signal Processing
62
發行號3
DOIs
出版狀態Published - 2010 三月 1

    指紋

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Hardware and Architecture
  • Surfaces, Coatings and Films

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