This paper proposes a double-edge-checking phase frequency detector (dec-PFD), designed in 0.35- μm CMOS process with 3-V supply voltage. Consisting of four-states without feedback paths, the dec-PFD can avoid U P and DOWN signals from rising to high at the same time and thus solve current mismatch problem with 3-ps dead-zone in the phase detection. The maximum operating frequency of the PFD is 4.78 GHz. Simulated results are presented to demonstrate the capability of phase detection of the circuit.
|出版狀態||Published - 2004 十二月 1|
|事件||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan|
持續時間: 2004 十二月 6 → 2004 十二月 9
|Other||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology|
|期間||04-12-06 → 04-12-09|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering