A 3-PS dead-zone double-edge-checking phase-frequency-detector with 4.78 GHz operating frequencies

Chien Ping Chou, Zhi-Ming Lin, Jun Da Chen

研究成果: Paper同行評審

6 引文 斯高帕斯(Scopus)

摘要

This paper proposes a double-edge-checking phase frequency detector (dec-PFD), designed in 0.35- μm CMOS process with 3-V supply voltage. Consisting of four-states without feedback paths, the dec-PFD can avoid U P and DOWN signals from rising to high at the same time and thus solve current mismatch problem with 3-ps dead-zone in the phase detection. The maximum operating frequency of the PFD is 4.78 GHz. Simulated results are presented to demonstrate the capability of phase detection of the circuit.

原文English
頁面937-940
頁數4
出版狀態Published - 2004 十二月 1
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 2004 十二月 62004 十二月 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家Taiwan
城市Tainan
期間04-12-0604-12-09

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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