A 12 bit direct level-signal transition based pipelined analog-to-digital converter

T. Y. Hsu, Zhi-Ming Lin

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters, we use a direct level-signal transition technique to replace the traditional digital-to-analog converter. The designed ADC consumes 43 mW power from a 1.8 V power supply. Simulated static DNL and INL errors are 0.5 LSB and 0.73 LSB, respectively. Compared with the traditional ADCs, our method can reduce up to 80% of transistor numbers.

原文English
主出版物標題IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
頁面881-884
頁數4
DOIs
出版狀態Published - 2007 十二月 1
事件IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan
持續時間: 2007 十二月 202007 十二月 22

出版系列

名字IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Other

OtherIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
國家Taiwan
城市Tainan
期間07-12-2007-12-22

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

指紋 深入研究「A 12 bit direct level-signal transition based pipelined analog-to-digital converter」主題。共同形成了獨特的指紋。

  • 引用此

    Hsu, T. Y., & Lin, Z-M. (2007). A 12 bit direct level-signal transition based pipelined analog-to-digital converter. 於 IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 (頁 881-884). [4450266] (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007). https://doi.org/10.1109/EDSSC.2007.4450266