Abstract
This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.
Original language | English |
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Pages (from-to) | 623-629 |
Number of pages | 7 |
Journal | IEEE Transactions on Consumer Electronics |
Volume | 44 |
Issue number | 3 |
DOIs | |
Publication status | Published - 1998 Dec 1 |
All Science Journal Classification (ASJC) codes
- Media Technology
- Electrical and Electronic Engineering