VLSI implementation of the motion estimator with two-dimensional data-reuse

Yeong Kang Lai, Yeong-Lin Lai, Yuan Chen Liu, Liang Gee Chen

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

Original languageEnglish
Pages (from-to)623-629
Number of pages7
JournalIEEE Transactions on Consumer Electronics
Volume44
Issue number3
DOIs
Publication statusPublished - 1998 Dec 1

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Shift registers
Pixels
Throughput
Hardware
Data storage equipment
Processing

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Electrical and Electronic Engineering

Cite this

Lai, Yeong Kang ; Lai, Yeong-Lin ; Liu, Yuan Chen ; Chen, Liang Gee. / VLSI implementation of the motion estimator with two-dimensional data-reuse. In: IEEE Transactions on Consumer Electronics. 1998 ; Vol. 44, No. 3. pp. 623-629.
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VLSI implementation of the motion estimator with two-dimensional data-reuse. / Lai, Yeong Kang; Lai, Yeong-Lin; Liu, Yuan Chen; Chen, Liang Gee.

In: IEEE Transactions on Consumer Electronics, Vol. 44, No. 3, 01.12.1998, p. 623-629.

Research output: Contribution to journalArticle

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