Abstract
This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.
| Original language | English |
|---|---|
| Pages (from-to) | 623-629 |
| Number of pages | 7 |
| Journal | IEEE Transactions on Consumer Electronics |
| Volume | 44 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 1998 Dec 1 |
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All Science Journal Classification (ASJC) codes
- Media Technology
- Electrical and Electronic Engineering
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VLSI implementation of the motion estimator with two-dimensional data-reuse. / Lai, Yeong Kang; Lai, Yeong-Lin; Liu, Yuan Chen; Chen, Liang Gee.
In: IEEE Transactions on Consumer Electronics, Vol. 44, No. 3, 01.12.1998, p. 623-629.Research output: Contribution to journal › Article
TY - JOUR
T1 - VLSI implementation of the motion estimator with two-dimensional data-reuse
AU - Lai, Yeong Kang
AU - Lai, Yeong-Lin
AU - Liu, Yuan Chen
AU - Chen, Liang Gee
PY - 1998/12/1
Y1 - 1998/12/1
N2 - This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.
AB - This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.
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UR - http://www.scopus.com/inward/citedby.url?scp=0032141487&partnerID=8YFLogxK
U2 - 10.1109/30.713173
DO - 10.1109/30.713173
M3 - Article
AN - SCOPUS:0032141487
VL - 44
SP - 623
EP - 629
JO - IEEE Transactions on Consumer Electronics
JF - IEEE Transactions on Consumer Electronics
SN - 0098-3063
IS - 3
ER -