VLSI implementation of a DWT architecture

Tinku Acharya, Po Yueh Chen

Research output: Contribution to journalConference article

19 Citations (Scopus)

Abstract

In this paper, we presented the VLSI implementation and the simulation results of a systolic architecture for Discrete Wavelet Transform (DWT). This architecture is suitable for both decomposition and reconstruction of signals. The hardware utilization of the architecture is 100% unlike many other existing solutions in the literature.

Original languageEnglish
Pages (from-to)272-275
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
Publication statusPublished - 1998 Jan 1
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: 1998 May 311998 Jun 3

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Discrete wavelet transforms
Decomposition
Hardware

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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title = "VLSI implementation of a DWT architecture",
abstract = "In this paper, we presented the VLSI implementation and the simulation results of a systolic architecture for Discrete Wavelet Transform (DWT). This architecture is suitable for both decomposition and reconstruction of signals. The hardware utilization of the architecture is 100{\%} unlike many other existing solutions in the literature.",
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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
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VLSI implementation of a DWT architecture. / Acharya, Tinku; Chen, Po Yueh.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 01.01.1998, p. 272-275.

Research output: Contribution to journalConference article

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