In this paper, we presented the VLSI implementation and the simulation results of a systolic architecture for Discrete Wavelet Transform (DWT). This architecture is suitable for both decomposition and reconstruction of signals. The hardware utilization of the architecture is 100% unlike many other existing solutions in the literature.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1998 Jan 1|
|Event||Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA|
Duration: 1998 May 31 → 1998 Jun 3
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering