Using the gate-diffusion input technique for low-power programmable logic array design

Shou Hung Chiu, Kai Cheng Wei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel low-power programmable logic array (PLA) structure based on gate diffusion input (GDI) is presented. The GDI technique allows reducing power consumption, propagation delay, and area of digital circuits. It also maintains low complexity of circuit design. In this chapter, we use the GDI technique to modify Kwang's PLAs. The conditional evaluation circuit in all product lines of Kwang's PLAs is replaced by a GDI circuit. To verify the proposed PLA, we use the MCNC PLA benchmark circuits to perform experiments. Simulation results show that the proposed scheme can reduce the number of transistors by 28.1 %, power consumption by 40.6 %, delay time by 15 %, and total power-delay product (PDP) by 49.5 % compared with Kwang's PLAs, which use the alu2 in MCNC benchmark for 0.18μm CMOS technology.

Original languageEnglish
Title of host publicationIntelligent Technologies and Engineering Systems
Pages601-607
Number of pages7
DOIs
Publication statusPublished - 2013 Aug 8
Event2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012 - Changhua, Taiwan
Duration: 2012 Dec 132012 Dec 15

Publication series

NameLecture Notes in Electrical Engineering
Volume234 LNEE
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

Other

Other2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012
CountryTaiwan
CityChanghua
Period12-12-1312-12-15

Fingerprint

Networks (circuits)
Electric power utilization
Digital circuits
Time delay
Transistors
Experiments

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering

Cite this

Chiu, S. H., & Wei, K. C. (2013). Using the gate-diffusion input technique for low-power programmable logic array design. In Intelligent Technologies and Engineering Systems (pp. 601-607). (Lecture Notes in Electrical Engineering; Vol. 234 LNEE). https://doi.org/10.1007/978-1-4614-6747-2_70
Chiu, Shou Hung ; Wei, Kai Cheng. / Using the gate-diffusion input technique for low-power programmable logic array design. Intelligent Technologies and Engineering Systems. 2013. pp. 601-607 (Lecture Notes in Electrical Engineering).
@inproceedings{3e475391aadb4ce897f928771cbf6350,
title = "Using the gate-diffusion input technique for low-power programmable logic array design",
abstract = "A novel low-power programmable logic array (PLA) structure based on gate diffusion input (GDI) is presented. The GDI technique allows reducing power consumption, propagation delay, and area of digital circuits. It also maintains low complexity of circuit design. In this chapter, we use the GDI technique to modify Kwang's PLAs. The conditional evaluation circuit in all product lines of Kwang's PLAs is replaced by a GDI circuit. To verify the proposed PLA, we use the MCNC PLA benchmark circuits to perform experiments. Simulation results show that the proposed scheme can reduce the number of transistors by 28.1 {\%}, power consumption by 40.6 {\%}, delay time by 15 {\%}, and total power-delay product (PDP) by 49.5 {\%} compared with Kwang's PLAs, which use the alu2 in MCNC benchmark for 0.18μm CMOS technology.",
author = "Chiu, {Shou Hung} and Wei, {Kai Cheng}",
year = "2013",
month = "8",
day = "8",
doi = "10.1007/978-1-4614-6747-2_70",
language = "English",
isbn = "9781461467465",
series = "Lecture Notes in Electrical Engineering",
pages = "601--607",
booktitle = "Intelligent Technologies and Engineering Systems",

}

Chiu, SH & Wei, KC 2013, Using the gate-diffusion input technique for low-power programmable logic array design. in Intelligent Technologies and Engineering Systems. Lecture Notes in Electrical Engineering, vol. 234 LNEE, pp. 601-607, 2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012, Changhua, Taiwan, 12-12-13. https://doi.org/10.1007/978-1-4614-6747-2_70

Using the gate-diffusion input technique for low-power programmable logic array design. / Chiu, Shou Hung; Wei, Kai Cheng.

Intelligent Technologies and Engineering Systems. 2013. p. 601-607 (Lecture Notes in Electrical Engineering; Vol. 234 LNEE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Using the gate-diffusion input technique for low-power programmable logic array design

AU - Chiu, Shou Hung

AU - Wei, Kai Cheng

PY - 2013/8/8

Y1 - 2013/8/8

N2 - A novel low-power programmable logic array (PLA) structure based on gate diffusion input (GDI) is presented. The GDI technique allows reducing power consumption, propagation delay, and area of digital circuits. It also maintains low complexity of circuit design. In this chapter, we use the GDI technique to modify Kwang's PLAs. The conditional evaluation circuit in all product lines of Kwang's PLAs is replaced by a GDI circuit. To verify the proposed PLA, we use the MCNC PLA benchmark circuits to perform experiments. Simulation results show that the proposed scheme can reduce the number of transistors by 28.1 %, power consumption by 40.6 %, delay time by 15 %, and total power-delay product (PDP) by 49.5 % compared with Kwang's PLAs, which use the alu2 in MCNC benchmark for 0.18μm CMOS technology.

AB - A novel low-power programmable logic array (PLA) structure based on gate diffusion input (GDI) is presented. The GDI technique allows reducing power consumption, propagation delay, and area of digital circuits. It also maintains low complexity of circuit design. In this chapter, we use the GDI technique to modify Kwang's PLAs. The conditional evaluation circuit in all product lines of Kwang's PLAs is replaced by a GDI circuit. To verify the proposed PLA, we use the MCNC PLA benchmark circuits to perform experiments. Simulation results show that the proposed scheme can reduce the number of transistors by 28.1 %, power consumption by 40.6 %, delay time by 15 %, and total power-delay product (PDP) by 49.5 % compared with Kwang's PLAs, which use the alu2 in MCNC benchmark for 0.18μm CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=84881042818&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84881042818&partnerID=8YFLogxK

U2 - 10.1007/978-1-4614-6747-2_70

DO - 10.1007/978-1-4614-6747-2_70

M3 - Conference contribution

AN - SCOPUS:84881042818

SN - 9781461467465

T3 - Lecture Notes in Electrical Engineering

SP - 601

EP - 607

BT - Intelligent Technologies and Engineering Systems

ER -

Chiu SH, Wei KC. Using the gate-diffusion input technique for low-power programmable logic array design. In Intelligent Technologies and Engineering Systems. 2013. p. 601-607. (Lecture Notes in Electrical Engineering). https://doi.org/10.1007/978-1-4614-6747-2_70