Abstract
A novel low-power programmable logic array (PLA) structure based on gate diffusion input (GDI) is presented. The GDI technique allows reducing power consumption, propagation delay, and area of digital circuits. It also maintains low complexity of circuit design. In this chapter, we use the GDI technique to modify Kwang's PLAs. The conditional evaluation circuit in all product lines of Kwang's PLAs is replaced by a GDI circuit. To verify the proposed PLA, we use the MCNC PLA benchmark circuits to perform experiments. Simulation results show that the proposed scheme can reduce the number of transistors by 28.1 %, power consumption by 40.6 %, delay time by 15 %, and total power-delay product (PDP) by 49.5 % compared with Kwang's PLAs, which use the alu2 in MCNC benchmark for 0.18μm CMOS technology.
| Original language | English |
|---|---|
| Title of host publication | Intelligent Technologies and Engineering Systems |
| Pages | 601-607 |
| Number of pages | 7 |
| DOIs | |
| Publication status | Published - 2013 Aug 8 |
| Event | 2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012 - Changhua, Taiwan Duration: 2012 Dec 13 → 2012 Dec 15 |
Publication series
| Name | Lecture Notes in Electrical Engineering |
|---|---|
| Volume | 234 LNEE |
| ISSN (Print) | 1876-1100 |
| ISSN (Electronic) | 1876-1119 |
Other
| Other | 2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012 |
|---|---|
| Country | Taiwan |
| City | Changhua |
| Period | 12-12-13 → 12-12-15 |
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All Science Journal Classification (ASJC) codes
- Industrial and Manufacturing Engineering
Cite this
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Using the gate-diffusion input technique for low-power programmable logic array design. / Chiu, Shou Hung; Wei, Kai Cheng.
Intelligent Technologies and Engineering Systems. 2013. p. 601-607 (Lecture Notes in Electrical Engineering; Vol. 234 LNEE).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Using the gate-diffusion input technique for low-power programmable logic array design
AU - Chiu, Shou Hung
AU - Wei, Kai Cheng
PY - 2013/8/8
Y1 - 2013/8/8
N2 - A novel low-power programmable logic array (PLA) structure based on gate diffusion input (GDI) is presented. The GDI technique allows reducing power consumption, propagation delay, and area of digital circuits. It also maintains low complexity of circuit design. In this chapter, we use the GDI technique to modify Kwang's PLAs. The conditional evaluation circuit in all product lines of Kwang's PLAs is replaced by a GDI circuit. To verify the proposed PLA, we use the MCNC PLA benchmark circuits to perform experiments. Simulation results show that the proposed scheme can reduce the number of transistors by 28.1 %, power consumption by 40.6 %, delay time by 15 %, and total power-delay product (PDP) by 49.5 % compared with Kwang's PLAs, which use the alu2 in MCNC benchmark for 0.18μm CMOS technology.
AB - A novel low-power programmable logic array (PLA) structure based on gate diffusion input (GDI) is presented. The GDI technique allows reducing power consumption, propagation delay, and area of digital circuits. It also maintains low complexity of circuit design. In this chapter, we use the GDI technique to modify Kwang's PLAs. The conditional evaluation circuit in all product lines of Kwang's PLAs is replaced by a GDI circuit. To verify the proposed PLA, we use the MCNC PLA benchmark circuits to perform experiments. Simulation results show that the proposed scheme can reduce the number of transistors by 28.1 %, power consumption by 40.6 %, delay time by 15 %, and total power-delay product (PDP) by 49.5 % compared with Kwang's PLAs, which use the alu2 in MCNC benchmark for 0.18μm CMOS technology.
UR - http://www.scopus.com/inward/record.url?scp=84881042818&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84881042818&partnerID=8YFLogxK
U2 - 10.1007/978-1-4614-6747-2_70
DO - 10.1007/978-1-4614-6747-2_70
M3 - Conference contribution
AN - SCOPUS:84881042818
SN - 9781461467465
T3 - Lecture Notes in Electrical Engineering
SP - 601
EP - 607
BT - Intelligent Technologies and Engineering Systems
ER -