Abstract
This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.
Original language | English |
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Title of host publication | Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 |
Pages | 347-350 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2010 Nov 8 |
Event | 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan Duration: 2010 Apr 26 → 2010 Apr 29 |
Other
Other | 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 |
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Country | Taiwan |
City | Hsin Chu |
Period | 10-04-26 → 10-04-29 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering