Abstract
This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 |
| Pages | 347-350 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2010 Nov 8 |
| Event | 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan Duration: 2010 Apr 26 → 2010 Apr 29 |
Other
| Other | 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 |
|---|---|
| Country | Taiwan |
| City | Hsin Chu |
| Period | 10-04-26 → 10-04-29 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
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Using the charge recycling technique for low power PLA design. / Xiao, Chiuan T.; wei, kai-cheng.
Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. 2010. p. 347-350 5496760.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Using the charge recycling technique for low power PLA design
AU - Xiao, Chiuan T.
AU - wei, kai-cheng
PY - 2010/11/8
Y1 - 2010/11/8
N2 - This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.
AB - This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.
UR - http://www.scopus.com/inward/record.url?scp=78049379000&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78049379000&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2010.5496760
DO - 10.1109/VDAT.2010.5496760
M3 - Conference contribution
AN - SCOPUS:78049379000
SN - 9781424452712
SP - 347
EP - 350
BT - Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
ER -