Using the charge recycling technique for low power PLA design

Chiuan T. Xiao, kai-cheng wei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.

Original languageEnglish
Title of host publicationProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Pages347-350
Number of pages4
DOIs
Publication statusPublished - 2010 Nov 8
Event2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan
Duration: 2010 Apr 262010 Apr 29

Other

Other2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
CountryTaiwan
CityHsin Chu
Period10-04-2610-04-29

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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