Using the charge recycling technique for low power PLA design

Chiuan T. Xiao; kai-cheng wei

doi:10.1109/VDAT.2010.5496760

Using the charge recycling technique for low power PLA design

Chiuan T. Xiao, kai-cheng wei

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.

Original language	English
Title of host publication	Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Pages	347-350
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2010.5496760
Publication status	Published - 2010 Nov 8
Event	2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan Duration: 2010 Apr 26 → 2010 Apr 29

Other

Other	2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Country	Taiwan
City	Hsin Chu
Period	10-04-26 → 10-04-29

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

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title = "Using the charge recycling technique for low power PLA design",

abstract = "This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.",

author = "Xiao, {Chiuan T.} and kai-cheng wei",

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pages = "347--350",

booktitle = "Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010",

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AU - Xiao, Chiuan T.

AU - wei, kai-cheng

PY - 2010/11/8

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N2 - This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.

AB - This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.

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BT - Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

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