Token scan cell for low power testing

Tsung-Chu Huang, K. J. Lee

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A multiphase clocking technique is presented for reducing the test power for scan-based circuits. A novel scan cell design called the token scan cell is developed, which combines a phase-generating flip-flop and a data flip-flop to overcome the inter-phase skew and clock routing problems. Experimental results show that on average ∼87% of the data transition count during scanning is reduced. For many circuits with long chains, a reduction of >98% can even be achieved.

Original languageEnglish
Pages (from-to)678-679
Number of pages2
JournalElectronics Letters
Volume37
Issue number11
DOIs
Publication statusPublished - 2001 May 24

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Flip flop circuits
Networks (circuits)
Testing
Clocks
Scanning

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Huang, Tsung-Chu ; Lee, K. J. / Token scan cell for low power testing. In: Electronics Letters. 2001 ; Vol. 37, No. 11. pp. 678-679.
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Token scan cell for low power testing. / Huang, Tsung-Chu; Lee, K. J.

In: Electronics Letters, Vol. 37, No. 11, 24.05.2001, p. 678-679.

Research output: Contribution to journalArticle

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