Three-transistor DRAM-based content addressable memory design for reliability and area efficiency

Wei Ning Hsu; Tsu Hsin Wu; Tsung Chu Huang

doi:10.1109/MTDT.2009.17

Three-transistor DRAM-based content addressable memory design for reliability and area efficiency

Wei Ning Hsu, Tsu Hsin Wu, Tsung Chu Huang

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content addressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability. A novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. From a variety of postlayout SPICE simulations, the search-match delay time cab be controlled under typical DRAM-based CAM level and the area efficient can be improved by almost double.

Original language	English
Title of host publication	Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Pages	38-43
Number of pages	6
DOIs	https://doi.org/10.1109/MTDT.2009.17
Publication status	Published - 2009
Event	2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 - Hsinchu, Taiwan Duration: 2009 Aug 31 → 2009 Sep 2

Publication series

Name	Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

Other

Other	2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Country	Taiwan
City	Hsinchu
Period	09-08-31 → 09-09-02

All Science Journal Classification (ASJC) codes

Computational Theory and Mathematics
Computer Science Applications
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/MTDT.2009.17

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Hsu, W. N., Wu, T. H., & Huang, T. C. (2009). Three-transistor DRAM-based content addressable memory design for reliability and area efficiency. In Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 (pp. 38-43). [5279829] (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009). https://doi.org/10.1109/MTDT.2009.17

Hsu, Wei Ning ; Wu, Tsu Hsin ; Huang, Tsung Chu. / Three-transistor DRAM-based content addressable memory design for reliability and area efficiency. Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009. 2009. pp. 38-43 (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009).

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title = "Three-transistor DRAM-based content addressable memory design for reliability and area efficiency",

abstract = "Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content addressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability. A novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. From a variety of postlayout SPICE simulations, the search-match delay time cab be controlled under typical DRAM-based CAM level and the area efficient can be improved by almost double.",

author = "Hsu, {Wei Ning} and Wu, {Tsu Hsin} and Huang, {Tsung Chu}",

note = "Copyright: Copyright 2010 Elsevier B.V., All rights reserved.; 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 ; Conference date: 31-08-2009 Through 02-09-2009",

year = "2009",

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language = "English",

isbn = "9780769537979",

series = "Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009",

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Hsu, WN, Wu, TH & Huang, TC 2009, Three-transistor DRAM-based content addressable memory design for reliability and area efficiency. in Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009., 5279829, Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009, pp. 38-43, 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009, Hsinchu, Taiwan, 09-08-31. https://doi.org/10.1109/MTDT.2009.17

Three-transistor DRAM-based content addressable memory design for reliability and area efficiency. / Hsu, Wei Ning; Wu, Tsu Hsin; Huang, Tsung Chu.

Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009. 2009. p. 38-43 5279829 (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content addressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability. A novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. From a variety of postlayout SPICE simulations, the search-match delay time cab be controlled under typical DRAM-based CAM level and the area efficient can be improved by almost double.

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Hsu WN, Wu TH, Huang TC. Three-transistor DRAM-based content addressable memory design for reliability and area efficiency. In Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009. 2009. p. 38-43. 5279829. (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009). https://doi.org/10.1109/MTDT.2009.17