Three-transistor DRAM-based content addressable memory design for reliability and area efficiency

Wei Ning Hsu, Tsu Hsin Wu, Tsung Chu Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content addressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability. A novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. From a variety of postlayout SPICE simulations, the search-match delay time cab be controlled under typical DRAM-based CAM level and the area efficient can be improved by almost double.

Original languageEnglish
Title of host publicationProceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Pages38-43
Number of pages6
DOIs
Publication statusPublished - 2009 Dec 25
Event2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 - Hsinchu, Taiwan
Duration: 2009 Aug 312009 Sep 2

Publication series

NameProceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

Other

Other2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
CountryTaiwan
CityHsinchu
Period09-08-3109-09-02

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All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Computer Science Applications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Hsu, W. N., Wu, T. H., & Huang, T. C. (2009). Three-transistor DRAM-based content addressable memory design for reliability and area efficiency. In Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 (pp. 38-43). [5279829] (Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009). https://doi.org/10.1109/MTDT.2009.17