TY - GEN
T1 - Three-transistor DRAM-based content addressable memory design for reliability and area efficiency
AU - Hsu, Wei Ning
AU - Wu, Tsu Hsin
AU - Huang, Tsung Chu
N1 - Copyright:
Copyright 2010 Elsevier B.V., All rights reserved.
PY - 2009
Y1 - 2009
N2 - Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content addressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability. A novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. From a variety of postlayout SPICE simulations, the search-match delay time cab be controlled under typical DRAM-based CAM level and the area efficient can be improved by almost double.
AB - Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content addressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability. A novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. From a variety of postlayout SPICE simulations, the search-match delay time cab be controlled under typical DRAM-based CAM level and the area efficient can be improved by almost double.
UR - http://www.scopus.com/inward/record.url?scp=72349088260&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=72349088260&partnerID=8YFLogxK
U2 - 10.1109/MTDT.2009.17
DO - 10.1109/MTDT.2009.17
M3 - Conference contribution
AN - SCOPUS:72349088260
SN - 9780769537979
T3 - Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
SP - 38
EP - 43
BT - Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
T2 - 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
Y2 - 31 August 2009 through 2 September 2009
ER -