The solder joint reliability assessment of a wafer level CSP package

Kuan Jung Chung, Chih Hao Tseng, Liyu Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A WLCSP package consists of 2.2 × 2.2 mm 2 silicon die, polyimide-based substrate, and 5 × 5 array of solder balls was used as the test vehicle to evaluate its solder joint reliability. Both package level tests with respect to precondition test, temperature cycling test, unbiased highly accelerated stress test (UHAST), and high temperature storage life (HTSL) test and board level tests regarding temperature cycling test have been included in the test plan. Two different lead free solder ball materials (SAC1205 vs. SAC105), under bump metallurgy (Ti/NiV/Cu vs. plated Cu), and die thicknesses (406 μm vs. 356 μm) were assessed. The test results for the package level assessment present that the test vehicle past criteria for all of these required tests. The test results of temperature cycling (-40°C ∼125°C) for the board level assessment show that these controlled variables have unlike performance in the solder joint reliability (SJR) of the WL-CSP package. The SAC105 shows better solder joint reliability performance than that of SAC1205 to provide 13 % improvement in characteristic life (Weibull distribution). The thick die (406 μm) shows statistically better SJR performance than that of thin die (356 m) to sustain 10% increase in characteristic life (Weibull distribution). On the other hand, standard Ti/NiV/Cu UBM presents statistically equivalent SJR performance as plated Cu in characteristic life. As the results, package design factors of the solder alloy and die thickness play obvious roles in solder joint reliability compared to the factor of UBM. Generally speaking, the WL-CSP package presents appropriate solder joint reliability according to the test results.

Original languageEnglish
Title of host publication2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2011
Pages370-372
Number of pages3
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2011 - Taipei, Taiwan
Duration: 2011 Oct 182011 Oct 21

Other

Other2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2011
CountryTaiwan
CityTaipei
Period11-10-1811-10-21

Fingerprint

Soldering alloys
Weibull distribution
Temperature
Metallurgy
Polyimides
Silicon
Substrates

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Chung, K. J., Tseng, C. H., & Yang, L. (2011). The solder joint reliability assessment of a wafer level CSP package. In 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2011 (pp. 370-372). [6117252] https://doi.org/10.1109/IMPACT.2011.6117252
Chung, Kuan Jung ; Tseng, Chih Hao ; Yang, Liyu. / The solder joint reliability assessment of a wafer level CSP package. 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2011. 2011. pp. 370-372
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abstract = "A WLCSP package consists of 2.2 × 2.2 mm 2 silicon die, polyimide-based substrate, and 5 × 5 array of solder balls was used as the test vehicle to evaluate its solder joint reliability. Both package level tests with respect to precondition test, temperature cycling test, unbiased highly accelerated stress test (UHAST), and high temperature storage life (HTSL) test and board level tests regarding temperature cycling test have been included in the test plan. Two different lead free solder ball materials (SAC1205 vs. SAC105), under bump metallurgy (Ti/NiV/Cu vs. plated Cu), and die thicknesses (406 μm vs. 356 μm) were assessed. The test results for the package level assessment present that the test vehicle past criteria for all of these required tests. The test results of temperature cycling (-40°C ∼125°C) for the board level assessment show that these controlled variables have unlike performance in the solder joint reliability (SJR) of the WL-CSP package. The SAC105 shows better solder joint reliability performance than that of SAC1205 to provide 13 {\%} improvement in characteristic life (Weibull distribution). The thick die (406 μm) shows statistically better SJR performance than that of thin die (356 m) to sustain 10{\%} increase in characteristic life (Weibull distribution). On the other hand, standard Ti/NiV/Cu UBM presents statistically equivalent SJR performance as plated Cu in characteristic life. As the results, package design factors of the solder alloy and die thickness play obvious roles in solder joint reliability compared to the factor of UBM. Generally speaking, the WL-CSP package presents appropriate solder joint reliability according to the test results.",
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Chung, KJ, Tseng, CH & Yang, L 2011, The solder joint reliability assessment of a wafer level CSP package. in 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2011., 6117252, pp. 370-372, 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2011, Taipei, Taiwan, 11-10-18. https://doi.org/10.1109/IMPACT.2011.6117252

The solder joint reliability assessment of a wafer level CSP package. / Chung, Kuan Jung; Tseng, Chih Hao; Yang, Liyu.

2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2011. 2011. p. 370-372 6117252.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chung KJ, Tseng CH, Yang L. The solder joint reliability assessment of a wafer level CSP package. In 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2011. 2011. p. 370-372. 6117252 https://doi.org/10.1109/IMPACT.2011.6117252