For high speed multiplier implementation, the recursive architecture is a parallel and modular approach with low complexity. However, compared to the conventional array multiplier, it costs more area due to the interconnection between sub-modules. In this study, the multiplexer based multiplier is adopted as the lower-level multiplier in the recursive architecture because it outperforms the conventional array multiplier in terms of speed, area, and power consumption. To further improve the speed performance, the proposed hybrid architecture exploits the carry-select adders (CSL) for partial products accumulation. The design is synthesized using TSMC 0.18μm standard cell process. According to the experimental results, the propagation delay is reduced by 20.5% and 40.9% respectively, compared to the optimized mux-multiplier and the conventional array multiplier. In addition, we reduce the proposed architecture to a partially truncated circuit for error tolerant applications. Without affecting the speed, both the power consumption and circuit area are further reduced by 25% approximately.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Computer Networks and Communications
- Electrical and Electronic Engineering