The new architecture of radix-4 Chinese abacus adder

Shu Chung Yi, Kun Tse Lee, Jin Jia Chen, Chien Hung Lin, Chuen Ching Wang, Chin Fa Hsieh, Chih Yung Lu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22%, 17%, and 14% less than those of CLA adders for 0.35μm, 0.25μm, and 0.18μm technologies, respectively. The power consumption of the abacus adders are 30%, 34%, and 60% less than those of CLA adders for 0.35μm, 0.25μm, and 0.18μm technologies, respectively. The use of Chinese abacus approach results a competitive technique with respect to conventional fast adder.

Original languageEnglish
Title of host publication36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Number of pages1
DOIs
Publication statusPublished - 2006 Nov 21
Event36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 - Singapore, Singapore
Duration: 2006 May 172006 May 20

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
CountrySingapore
CitySingapore
Period06-05-1706-05-20

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All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Mathematics(all)

Cite this

Yi, S. C., Lee, K. T., Chen, J. J., Lin, C. H., Wang, C. C., Hsieh, C. F., & Lu, C. Y. (2006). The new architecture of radix-4 Chinese abacus adder. In 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 [1623964] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2006.41