The new architecture of radix-4 Chinese abacus adder

Shu Chung Yi, Kun Tse Lee, Jin Jia Chen, Chien Hung Lin, Chuen Ching Wang, Chin Fa Hsieh, Chih Yung Lu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22%, 17%, and 14% less than those of CLA adders for 0.35μm, 0.25μm, and 0.18μm technologies, respectively. The power consumption of the abacus adders are 30%, 34%, and 60% less than those of CLA adders for 0.35μm, 0.25μm, and 0.18μm technologies, respectively. The use of Chinese abacus approach results a competitive technique with respect to conventional fast adder.

Original languageEnglish
Title of host publication36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Number of pages1
DOIs
Publication statusPublished - 2006 Nov 21
Event36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 - Singapore, Singapore
Duration: 2006 May 172006 May 20

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
CountrySingapore
CitySingapore
Period06-05-1706-05-20

Fingerprint

Abacus
Adders
Look-ahead
Power Consumption
High Speed
Architecture
Propagation
Electric power utilization
Simulation

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Mathematics(all)

Cite this

Yi, S. C., Lee, K. T., Chen, J. J., Lin, C. H., Wang, C. C., Hsieh, C. F., & Lu, C. Y. (2006). The new architecture of radix-4 Chinese abacus adder. In 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006 [1623964] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2006.41
Yi, Shu Chung ; Lee, Kun Tse ; Chen, Jin Jia ; Lin, Chien Hung ; Wang, Chuen Ching ; Hsieh, Chin Fa ; Lu, Chih Yung. / The new architecture of radix-4 Chinese abacus adder. 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006. 2006. (Proceedings of The International Symposium on Multiple-Valued Logic).
@inproceedings{17e81ea9d69f46528d952e649428c8e9,
title = "The new architecture of radix-4 Chinese abacus adder",
abstract = "In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22{\%}, 17{\%}, and 14{\%} less than those of CLA adders for 0.35μm, 0.25μm, and 0.18μm technologies, respectively. The power consumption of the abacus adders are 30{\%}, 34{\%}, and 60{\%} less than those of CLA adders for 0.35μm, 0.25μm, and 0.18μm technologies, respectively. The use of Chinese abacus approach results a competitive technique with respect to conventional fast adder.",
author = "Yi, {Shu Chung} and Lee, {Kun Tse} and Chen, {Jin Jia} and Lin, {Chien Hung} and Wang, {Chuen Ching} and Hsieh, {Chin Fa} and Lu, {Chih Yung}",
year = "2006",
month = "11",
day = "21",
doi = "10.1109/ISMVL.2006.41",
language = "English",
isbn = "0769525326",
series = "Proceedings of The International Symposium on Multiple-Valued Logic",
booktitle = "36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006",

}

Yi, SC, Lee, KT, Chen, JJ, Lin, CH, Wang, CC, Hsieh, CF & Lu, CY 2006, The new architecture of radix-4 Chinese abacus adder. in 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006., 1623964, Proceedings of The International Symposium on Multiple-Valued Logic, 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006, Singapore, Singapore, 06-05-17. https://doi.org/10.1109/ISMVL.2006.41

The new architecture of radix-4 Chinese abacus adder. / Yi, Shu Chung; Lee, Kun Tse; Chen, Jin Jia; Lin, Chien Hung; Wang, Chuen Ching; Hsieh, Chin Fa; Lu, Chih Yung.

36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006. 2006. 1623964 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - The new architecture of radix-4 Chinese abacus adder

AU - Yi, Shu Chung

AU - Lee, Kun Tse

AU - Chen, Jin Jia

AU - Lin, Chien Hung

AU - Wang, Chuen Ching

AU - Hsieh, Chin Fa

AU - Lu, Chih Yung

PY - 2006/11/21

Y1 - 2006/11/21

N2 - In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22%, 17%, and 14% less than those of CLA adders for 0.35μm, 0.25μm, and 0.18μm technologies, respectively. The power consumption of the abacus adders are 30%, 34%, and 60% less than those of CLA adders for 0.35μm, 0.25μm, and 0.18μm technologies, respectively. The use of Chinese abacus approach results a competitive technique with respect to conventional fast adder.

AB - In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22%, 17%, and 14% less than those of CLA adders for 0.35μm, 0.25μm, and 0.18μm technologies, respectively. The power consumption of the abacus adders are 30%, 34%, and 60% less than those of CLA adders for 0.35μm, 0.25μm, and 0.18μm technologies, respectively. The use of Chinese abacus approach results a competitive technique with respect to conventional fast adder.

UR - http://www.scopus.com/inward/record.url?scp=33751066735&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33751066735&partnerID=8YFLogxK

U2 - 10.1109/ISMVL.2006.41

DO - 10.1109/ISMVL.2006.41

M3 - Conference contribution

AN - SCOPUS:33751066735

SN - 0769525326

SN - 9780769525327

T3 - Proceedings of The International Symposium on Multiple-Valued Logic

BT - 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006

ER -

Yi SC, Lee KT, Chen JJ, Lin CH, Wang CC, Hsieh CF et al. The new architecture of radix-4 Chinese abacus adder. In 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006. 2006. 1623964. (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2006.41