Branch prediction is a key mechanism to boost the system performance of a superscalar processor. Though the prediction accuracy rate becomes higher and higher, the mispredicitons still lead to significant performance losses in a wide-issue deep-pipelined superscalar. To address the problem, the technique of multipath execution has been proposed previously, which is capable of executing both paths whenever a lower-confidence conditional branch is encountered. However, because the instructions from different paths share a single register update unit (RUU), they are interleaved in the RUU. In consequence, when a conditional branch is resolved and the instructions on the wrong paths are squashed, all the entries in the resulting holes cannot be reused until they are reclaimed at the commit stage. Since the RUU size is crucial to the performance, it is interesting to know how much can we speedup the performance if the squashed RUU entries can be reused as soon as possible. We have proposed a simple mechanism with very limited hardware resources to achieve this goal. Finally the preliminary simulation results are presented.