Abstract
We propose a method for synthesizing from a behavioral description in a hardware description language. The description provides two mechanisms - edge-triggered and level-sensitive - for process synchronization and interface designs, which characterize most control-dominated circuits. They are usually asynchronous with the system clock. Conventional control-step-based, scheduling-and-allocation approaches for high-level synthesis are implicitly synchronous and, therefore, cannot correctly produce a structure that exhibits the exact (timing) behavior in the presence of such asynchrony. We construct first a mixed synchronous/asynchronous state graph to capture the described behavior. Then, according to a set of rules, our algorithm transforms the graph into a completely synchronous one, from which synthesis to structure has been proven easy. Simulation of a number of circuits has confirmed that the synthesized structures exhibit identical behavior (in terms of both functionality and timing) as the original description.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the European Design and Test Conference |
| Editors | Anon |
| Publisher | Publ by IEEE |
| Pages | 277-281 |
| Number of pages | 5 |
| ISBN (Print) | 0818654112 |
| Publication status | Published - 1994 Jan 1 |
| Event | Proceedings of the European Design and Test Conference - Paris, Fr Duration: 1994 Feb 28 → 1994 Mar 3 |
Publication series
| Name | Proceedings of the European Design and Test Conference |
|---|
Other
| Other | Proceedings of the European Design and Test Conference |
|---|---|
| City | Paris, Fr |
| Period | 94-02-28 → 94-03-03 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
}
Synthesis method for mixed synchronous/asynchronous behavior. / Wu, Tsung Yi; Tien, Tzu Chie; Wu, Allen C.H.; Lin, Youn Long.
Proceedings of the European Design and Test Conference. ed. / Anon. Publ by IEEE, 1994. p. 277-281 (Proceedings of the European Design and Test Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Synthesis method for mixed synchronous/asynchronous behavior
AU - Wu, Tsung Yi
AU - Tien, Tzu Chie
AU - Wu, Allen C.H.
AU - Lin, Youn Long
PY - 1994/1/1
Y1 - 1994/1/1
N2 - We propose a method for synthesizing from a behavioral description in a hardware description language. The description provides two mechanisms - edge-triggered and level-sensitive - for process synchronization and interface designs, which characterize most control-dominated circuits. They are usually asynchronous with the system clock. Conventional control-step-based, scheduling-and-allocation approaches for high-level synthesis are implicitly synchronous and, therefore, cannot correctly produce a structure that exhibits the exact (timing) behavior in the presence of such asynchrony. We construct first a mixed synchronous/asynchronous state graph to capture the described behavior. Then, according to a set of rules, our algorithm transforms the graph into a completely synchronous one, from which synthesis to structure has been proven easy. Simulation of a number of circuits has confirmed that the synthesized structures exhibit identical behavior (in terms of both functionality and timing) as the original description.
AB - We propose a method for synthesizing from a behavioral description in a hardware description language. The description provides two mechanisms - edge-triggered and level-sensitive - for process synchronization and interface designs, which characterize most control-dominated circuits. They are usually asynchronous with the system clock. Conventional control-step-based, scheduling-and-allocation approaches for high-level synthesis are implicitly synchronous and, therefore, cannot correctly produce a structure that exhibits the exact (timing) behavior in the presence of such asynchrony. We construct first a mixed synchronous/asynchronous state graph to capture the described behavior. Then, according to a set of rules, our algorithm transforms the graph into a completely synchronous one, from which synthesis to structure has been proven easy. Simulation of a number of circuits has confirmed that the synthesized structures exhibit identical behavior (in terms of both functionality and timing) as the original description.
UR - http://www.scopus.com/inward/record.url?scp=0028115283&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0028115283&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0028115283
SN - 0818654112
T3 - Proceedings of the European Design and Test Conference
SP - 277
EP - 281
BT - Proceedings of the European Design and Test Conference
A2 - Anon, null
PB - Publ by IEEE
ER -