Synthesis method for mixed synchronous/asynchronous behavior

Tsung Yi Wu, Tzu Chie Tien, Allen C.H. Wu, Youn Long Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution


We propose a method for synthesizing from a behavioral description in a hardware description language. The description provides two mechanisms - edge-triggered and level-sensitive - for process synchronization and interface designs, which characterize most control-dominated circuits. They are usually asynchronous with the system clock. Conventional control-step-based, scheduling-and-allocation approaches for high-level synthesis are implicitly synchronous and, therefore, cannot correctly produce a structure that exhibits the exact (timing) behavior in the presence of such asynchrony. We construct first a mixed synchronous/asynchronous state graph to capture the described behavior. Then, according to a set of rules, our algorithm transforms the graph into a completely synchronous one, from which synthesis to structure has been proven easy. Simulation of a number of circuits has confirmed that the synthesized structures exhibit identical behavior (in terms of both functionality and timing) as the original description.

Original languageEnglish
Title of host publicationProceedings of the European Design and Test Conference
Editors Anon
PublisherPubl by IEEE
Number of pages5
ISBN (Print)0818654112
Publication statusPublished - 1994 Jan 1
EventProceedings of the European Design and Test Conference - Paris, Fr
Duration: 1994 Feb 281994 Mar 3

Publication series

NameProceedings of the European Design and Test Conference


OtherProceedings of the European Design and Test Conference
CityParis, Fr

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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