TY - GEN
T1 - Synthesis method for mixed synchronous/asynchronous behavior
AU - Wu, Tsung Yi
AU - Tien, Tzu Chie
AU - Wu, Allen C.H.
AU - Lin, Youn Long
PY - 1994/1/1
Y1 - 1994/1/1
N2 - We propose a method for synthesizing from a behavioral description in a hardware description language. The description provides two mechanisms - edge-triggered and level-sensitive - for process synchronization and interface designs, which characterize most control-dominated circuits. They are usually asynchronous with the system clock. Conventional control-step-based, scheduling-and-allocation approaches for high-level synthesis are implicitly synchronous and, therefore, cannot correctly produce a structure that exhibits the exact (timing) behavior in the presence of such asynchrony. We construct first a mixed synchronous/asynchronous state graph to capture the described behavior. Then, according to a set of rules, our algorithm transforms the graph into a completely synchronous one, from which synthesis to structure has been proven easy. Simulation of a number of circuits has confirmed that the synthesized structures exhibit identical behavior (in terms of both functionality and timing) as the original description.
AB - We propose a method for synthesizing from a behavioral description in a hardware description language. The description provides two mechanisms - edge-triggered and level-sensitive - for process synchronization and interface designs, which characterize most control-dominated circuits. They are usually asynchronous with the system clock. Conventional control-step-based, scheduling-and-allocation approaches for high-level synthesis are implicitly synchronous and, therefore, cannot correctly produce a structure that exhibits the exact (timing) behavior in the presence of such asynchrony. We construct first a mixed synchronous/asynchronous state graph to capture the described behavior. Then, according to a set of rules, our algorithm transforms the graph into a completely synchronous one, from which synthesis to structure has been proven easy. Simulation of a number of circuits has confirmed that the synthesized structures exhibit identical behavior (in terms of both functionality and timing) as the original description.
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M3 - Conference contribution
AN - SCOPUS:0028115283
SN - 0818654112
T3 - Proceedings of the European Design and Test Conference
SP - 277
EP - 281
BT - Proceedings of the European Design and Test Conference
A2 - Anon, null
PB - Publ by IEEE
T2 - Proceedings of the European Design and Test Conference
Y2 - 28 February 1994 through 3 March 1994
ER -