Abstract
This study investigates the possible hardware realization of the sum-of-product neural networks (SOPNN). A SOPNN is a memory-based neural network, whose output has a sum-of-product form. The neural network structure consists of several submodules, of which each receives inputs and generates a local output. The local outputs from several submodules are added up to generate an overall network output. In each submodule, each input variable is used to address a memory location. Outputs from several memory blocks in a submodule are multiplied together to form a local submodule output. To implement the structure using analog circuits, each digital input needs to be converted into an analog one by a D/A converter. The product of the outputs from the memory blocks can be computed using a cascade multiplier. These products are then added up. In this study, the possible hardware realization is investigated. Simulations using PSpice for the D/A converter, the multiplier, and the adder have been performed. An example with 4 inputs and 3 submodules has been simulated to test and evaluate the overall design. Results show that the performance of the circuit is good.
Original language | English |
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Pages | 167-172 |
Number of pages | 6 |
Publication status | Published - 1999 Dec 1 |
Event | Proceedings of the 1999 Artificial Neural Networks in Engineering Conference (ANNIE '99) - St. Louis, MO, USA Duration: 1999 Nov 7 → 1999 Nov 10 |
Other
Other | Proceedings of the 1999 Artificial Neural Networks in Engineering Conference (ANNIE '99) |
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City | St. Louis, MO, USA |
Period | 99-11-07 → 99-11-10 |
All Science Journal Classification (ASJC) codes
- Software