Spatial scanning-probe array system for silicon-on-insulator integrated circuits

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A spatial scanning-probe array system for silicon-on-insulator (SOI) integrated circuit is proposed in this paper. The operating fundamentals, specifications, and simulations are presented in this paper. The proposed system is designed to scan the circuit in order to examine the surface and detect die cracks. The post signal processing by using discrete wavelet transform (DWT) for scattered optical signal is also proposed and simulated.

Original languageEnglish
Title of host publication2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
Pages910-913
Number of pages4
DOIs
Publication statusPublished - 2008 Oct 27
Event2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS - Knoxville, TN, United States
Duration: 2008 Aug 102008 Aug 13

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
CountryUnited States
CityKnoxville, TN
Period08-08-1008-08-13

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Yang, W. R. (2008). Spatial scanning-probe array system for silicon-on-insulator integrated circuits. In 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS (pp. 910-913). [4616948] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2008.4616948