Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS

Shen Li Chen; Min Hua Lee; Tzung Shian Wu; Yi Sheng Lai; Chun Ju Lin; Hsun-Hsiang Chen

doi:10.1007/978-1-4614-6747-2_60

Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS

Shen Li Chen, Min Hua Lee, Tzung Shian Wu, Yi Sheng Lai, Chun Ju Lin, Hsun-Hsiang Chen

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

Latch-up (LU)/electrostatic discharge (ESD) protection inclinations of a high-voltage (HV) IC reliability are investigated in this chapter, where the test DUTs were fabricated by a 0.25 um 60 V BCD process. In order to effectively evaluate the LU and ESD reliabilities, the source-end layout in two manners were proposed and verified; all of them effectively improved the trigger voltage (V _t1) or the secondary breakdown current (I _t2) to enhance its ESD immunity. These two kinds of source-end layout are the P ⁺ of discrete distributed type and P⁺ of bulk-contact numbers varied type, while these two different layout methods have their own advantages and disadvantages. It can be concluded that the ESD immunity level or the trigger voltage (V _t1) decreasing of a device can be improved by the source-end layout optimization in an HV process. Then, in this work, by using some layout techniques to improve the important reliability robustness, these strategies will be easily used and without added any additional process or mask in an HV process technology.

Original language	English
Title of host publication	Intelligent Technologies and Engineering Systems
Pages	503-511
Number of pages	9
DOIs	https://doi.org/10.1007/978-1-4614-6747-2_60
Publication status	Published - 2013 Aug 8
Event	2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012 - Changhua, Taiwan Duration: 2012 Dec 13 → 2012 Dec 15

Publication series

Name	Lecture Notes in Electrical Engineering
Volume	234 LNEE
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

Other

Other	2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012
Country	Taiwan
City	Changhua
Period	12-12-13 → 12-12-15

All Science Journal Classification (ASJC) codes

Industrial and Manufacturing Engineering

Access to Document

10.1007/978-1-4614-6747-2_60

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title = "Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS",

abstract = "Latch-up (LU)/electrostatic discharge (ESD) protection inclinations of a high-voltage (HV) IC reliability are investigated in this chapter, where the test DUTs were fabricated by a 0.25 um 60 V BCD process. In order to effectively evaluate the LU and ESD reliabilities, the source-end layout in two manners were proposed and verified; all of them effectively improved the trigger voltage (V t1) or the secondary breakdown current (I t2) to enhance its ESD immunity. These two kinds of source-end layout are the P + of discrete distributed type and P+ of bulk-contact numbers varied type, while these two different layout methods have their own advantages and disadvantages. It can be concluded that the ESD immunity level or the trigger voltage (V t1) decreasing of a device can be improved by the source-end layout optimization in an HV process. Then, in this work, by using some layout techniques to improve the important reliability robustness, these strategies will be easily used and without added any additional process or mask in an HV process technology.",

author = "Chen, {Shen Li} and Lee, {Min Hua} and Wu, {Tzung Shian} and Lai, {Yi Sheng} and Lin, {Chun Ju} and Hsun-Hsiang Chen",

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Chen, SL, Lee, MH, Wu, TS, Lai, YS, Lin, CJ & Chen, H-H 2013, Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS. in Intelligent Technologies and Engineering Systems. Lecture Notes in Electrical Engineering, vol. 234 LNEE, pp. 503-511, 2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012, Changhua, Taiwan, 12-12-13. https://doi.org/10.1007/978-1-4614-6747-2_60

Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS. / Chen, Shen Li; Lee, Min Hua; Wu, Tzung Shian; Lai, Yi Sheng; Lin, Chun Ju; Chen, Hsun-Hsiang.

Intelligent Technologies and Engineering Systems. 2013. p. 503-511 (Lecture Notes in Electrical Engineering; Vol. 234 LNEE).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Chen, Hsun-Hsiang

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N2 - Latch-up (LU)/electrostatic discharge (ESD) protection inclinations of a high-voltage (HV) IC reliability are investigated in this chapter, where the test DUTs were fabricated by a 0.25 um 60 V BCD process. In order to effectively evaluate the LU and ESD reliabilities, the source-end layout in two manners were proposed and verified; all of them effectively improved the trigger voltage (V t1) or the secondary breakdown current (I t2) to enhance its ESD immunity. These two kinds of source-end layout are the P + of discrete distributed type and P+ of bulk-contact numbers varied type, while these two different layout methods have their own advantages and disadvantages. It can be concluded that the ESD immunity level or the trigger voltage (V t1) decreasing of a device can be improved by the source-end layout optimization in an HV process. Then, in this work, by using some layout techniques to improve the important reliability robustness, these strategies will be easily used and without added any additional process or mask in an HV process technology.

AB - Latch-up (LU)/electrostatic discharge (ESD) protection inclinations of a high-voltage (HV) IC reliability are investigated in this chapter, where the test DUTs were fabricated by a 0.25 um 60 V BCD process. In order to effectively evaluate the LU and ESD reliabilities, the source-end layout in two manners were proposed and verified; all of them effectively improved the trigger voltage (V t1) or the secondary breakdown current (I t2) to enhance its ESD immunity. These two kinds of source-end layout are the P + of discrete distributed type and P+ of bulk-contact numbers varied type, while these two different layout methods have their own advantages and disadvantages. It can be concluded that the ESD immunity level or the trigger voltage (V t1) decreasing of a device can be improved by the source-end layout optimization in an HV process. Then, in this work, by using some layout techniques to improve the important reliability robustness, these strategies will be easily used and without added any additional process or mask in an HV process technology.

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