Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS

Shen Li Chen, Min Hua Lee, Tzung Shian Wu, Yi Sheng Lai, Chun Ju Lin, Hsun-Hsiang Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Latch-up (LU)/electrostatic discharge (ESD) protection inclinations of a high-voltage (HV) IC reliability are investigated in this chapter, where the test DUTs were fabricated by a 0.25 um 60 V BCD process. In order to effectively evaluate the LU and ESD reliabilities, the source-end layout in two manners were proposed and verified; all of them effectively improved the trigger voltage (V t1) or the secondary breakdown current (I t2) to enhance its ESD immunity. These two kinds of source-end layout are the P + of discrete distributed type and P+ of bulk-contact numbers varied type, while these two different layout methods have their own advantages and disadvantages. It can be concluded that the ESD immunity level or the trigger voltage (V t1) decreasing of a device can be improved by the source-end layout optimization in an HV process. Then, in this work, by using some layout techniques to improve the important reliability robustness, these strategies will be easily used and without added any additional process or mask in an HV process technology.

Original languageEnglish
Title of host publicationIntelligent Technologies and Engineering Systems
Pages503-511
Number of pages9
DOIs
Publication statusPublished - 2013 Aug 8
Event2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012 - Changhua, Taiwan
Duration: 2012 Dec 132012 Dec 15

Publication series

NameLecture Notes in Electrical Engineering
Volume234 LNEE
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

Other

Other2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012
CountryTaiwan
CityChanghua
Period12-12-1312-12-15

Fingerprint

Electrostatic discharge
Electric potential
Masks

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering

Cite this

Chen, S. L., Lee, M. H., Wu, T. S., Lai, Y. S., Lin, C. J., & Chen, H-H. (2013). Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS. In Intelligent Technologies and Engineering Systems (pp. 503-511). (Lecture Notes in Electrical Engineering; Vol. 234 LNEE). https://doi.org/10.1007/978-1-4614-6747-2_60
Chen, Shen Li ; Lee, Min Hua ; Wu, Tzung Shian ; Lai, Yi Sheng ; Lin, Chun Ju ; Chen, Hsun-Hsiang. / Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS. Intelligent Technologies and Engineering Systems. 2013. pp. 503-511 (Lecture Notes in Electrical Engineering).
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Chen, SL, Lee, MH, Wu, TS, Lai, YS, Lin, CJ & Chen, H-H 2013, Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS. in Intelligent Technologies and Engineering Systems. Lecture Notes in Electrical Engineering, vol. 234 LNEE, pp. 503-511, 2012 1st International Conference on Intelligent Technologies and Engineering Systems, ICITES 2012, Changhua, Taiwan, 12-12-13. https://doi.org/10.1007/978-1-4614-6747-2_60

Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS. / Chen, Shen Li; Lee, Min Hua; Wu, Tzung Shian; Lai, Yi Sheng; Lin, Chun Ju; Chen, Hsun-Hsiang.

Intelligent Technologies and Engineering Systems. 2013. p. 503-511 (Lecture Notes in Electrical Engineering; Vol. 234 LNEE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chen SL, Lee MH, Wu TS, Lai YS, Lin CJ, Chen H-H. Source-end layouts on ESD/LU reliabilities in an HV 0.25 um 60 v nLDMOS. In Intelligent Technologies and Engineering Systems. 2013. p. 503-511. (Lecture Notes in Electrical Engineering). https://doi.org/10.1007/978-1-4614-6747-2_60