Register swapping schemes for low power execution

Po-Yueh Chen, Chiung Hsien Jen

Research output: Contribution to journalArticle

Abstract

For embedded systems, the power dissipation on buses has become an essential issue in recent years. Many real-time embedded processors, such as DSP processors, adopt the Harvard architecture in which the data and instruction buses are separated to avoid processing-speed degradation. The power dissipation on an instruction bus can be reduced if the switching activities between consecutive instructions on that bus are reduced. Two efficient algorithms, the greedy method and the dynamic programming based method, are proposed to swap commutative source register fields of adjacent instructions. The switching activities on the instruction bus are therefore reduced, without affecting the execution results. Experimental results show that the proposed schemes result in a reduction of as much as 21.43% in the switching activities of consecutive source register fields between commutative blocks. In addition, the proposed schemes can be conveniently integrated with other encoding schemes to further improve the power dissipation on an instruction bus.

Original languageEnglish
Pages (from-to)485-495
Number of pages11
JournalMicroprocessors and Microsystems
Volume38
Issue number5
DOIs
Publication statusPublished - 2014 Jan 1

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Energy dissipation
Dynamic programming
Embedded systems
Degradation
Processing

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

Cite this

Chen, Po-Yueh ; Jen, Chiung Hsien. / Register swapping schemes for low power execution. In: Microprocessors and Microsystems. 2014 ; Vol. 38, No. 5. pp. 485-495.
@article{b3b63468ebe04122ade9b03c9ae006d5,
title = "Register swapping schemes for low power execution",
abstract = "For embedded systems, the power dissipation on buses has become an essential issue in recent years. Many real-time embedded processors, such as DSP processors, adopt the Harvard architecture in which the data and instruction buses are separated to avoid processing-speed degradation. The power dissipation on an instruction bus can be reduced if the switching activities between consecutive instructions on that bus are reduced. Two efficient algorithms, the greedy method and the dynamic programming based method, are proposed to swap commutative source register fields of adjacent instructions. The switching activities on the instruction bus are therefore reduced, without affecting the execution results. Experimental results show that the proposed schemes result in a reduction of as much as 21.43{\%} in the switching activities of consecutive source register fields between commutative blocks. In addition, the proposed schemes can be conveniently integrated with other encoding schemes to further improve the power dissipation on an instruction bus.",
author = "Po-Yueh Chen and Jen, {Chiung Hsien}",
year = "2014",
month = "1",
day = "1",
doi = "10.1016/j.micpro.2014.03.001",
language = "English",
volume = "38",
pages = "485--495",
journal = "Microprocessors and Microsystems",
issn = "0141-9331",
publisher = "Elsevier",
number = "5",

}

Register swapping schemes for low power execution. / Chen, Po-Yueh; Jen, Chiung Hsien.

In: Microprocessors and Microsystems, Vol. 38, No. 5, 01.01.2014, p. 485-495.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Register swapping schemes for low power execution

AU - Chen, Po-Yueh

AU - Jen, Chiung Hsien

PY - 2014/1/1

Y1 - 2014/1/1

N2 - For embedded systems, the power dissipation on buses has become an essential issue in recent years. Many real-time embedded processors, such as DSP processors, adopt the Harvard architecture in which the data and instruction buses are separated to avoid processing-speed degradation. The power dissipation on an instruction bus can be reduced if the switching activities between consecutive instructions on that bus are reduced. Two efficient algorithms, the greedy method and the dynamic programming based method, are proposed to swap commutative source register fields of adjacent instructions. The switching activities on the instruction bus are therefore reduced, without affecting the execution results. Experimental results show that the proposed schemes result in a reduction of as much as 21.43% in the switching activities of consecutive source register fields between commutative blocks. In addition, the proposed schemes can be conveniently integrated with other encoding schemes to further improve the power dissipation on an instruction bus.

AB - For embedded systems, the power dissipation on buses has become an essential issue in recent years. Many real-time embedded processors, such as DSP processors, adopt the Harvard architecture in which the data and instruction buses are separated to avoid processing-speed degradation. The power dissipation on an instruction bus can be reduced if the switching activities between consecutive instructions on that bus are reduced. Two efficient algorithms, the greedy method and the dynamic programming based method, are proposed to swap commutative source register fields of adjacent instructions. The switching activities on the instruction bus are therefore reduced, without affecting the execution results. Experimental results show that the proposed schemes result in a reduction of as much as 21.43% in the switching activities of consecutive source register fields between commutative blocks. In addition, the proposed schemes can be conveniently integrated with other encoding schemes to further improve the power dissipation on an instruction bus.

UR - http://www.scopus.com/inward/record.url?scp=84903303931&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84903303931&partnerID=8YFLogxK

U2 - 10.1016/j.micpro.2014.03.001

DO - 10.1016/j.micpro.2014.03.001

M3 - Article

AN - SCOPUS:84903303931

VL - 38

SP - 485

EP - 495

JO - Microprocessors and Microsystems

JF - Microprocessors and Microsystems

SN - 0141-9331

IS - 5

ER -