Abstract
Traditionally, it is assumed that every variable in the input HDL (hardware description language) behavioral description needs to be held in a register; a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been shown effective for signal-flow-like computations such as various DSP algorithms. However, the same is not true for the synthesis of controldominated circuits, which usually have variables of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, some unclocked sequential networks or a combination of above. We identify the conditions in which the substitution is feasible. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register area minimization also generally leads to faster designs.
| Original language | English |
|---|---|
| Pages (from-to) | 1583-1587 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 15 |
| Issue number | 12 |
| DOIs | |
| Publication status | Published - 1996 Dec 1 |
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All Science Journal Classification (ASJC) codes
- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
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Register minimization beyond sharing among variables. / Wu, Tsung-Yi; Lin, Youn Long.
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 12, 01.12.1996, p. 1583-1587.Research output: Contribution to journal › Article
TY - JOUR
T1 - Register minimization beyond sharing among variables
AU - Wu, Tsung-Yi
AU - Lin, Youn Long
PY - 1996/12/1
Y1 - 1996/12/1
N2 - Traditionally, it is assumed that every variable in the input HDL (hardware description language) behavioral description needs to be held in a register; a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been shown effective for signal-flow-like computations such as various DSP algorithms. However, the same is not true for the synthesis of controldominated circuits, which usually have variables of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, some unclocked sequential networks or a combination of above. We identify the conditions in which the substitution is feasible. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register area minimization also generally leads to faster designs.
AB - Traditionally, it is assumed that every variable in the input HDL (hardware description language) behavioral description needs to be held in a register; a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been shown effective for signal-flow-like computations such as various DSP algorithms. However, the same is not true for the synthesis of controldominated circuits, which usually have variables of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, some unclocked sequential networks or a combination of above. We identify the conditions in which the substitution is feasible. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register area minimization also generally leads to faster designs.
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U2 - 10.1109/43.552092
DO - 10.1109/43.552092
M3 - Article
VL - 15
SP - 1583
EP - 1587
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 12
ER -