Register minimization beyond sharing among variables

Tsung-Yi Wu, Youn Long Lin

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Traditionally, it is assumed that every variable in the input HDL (hardware description language) behavioral description needs to be held in a register; a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been shown effective for signal-flow-like computations such as various DSP algorithms. However, the same is not true for the synthesis of controldominated circuits, which usually have variables of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, some unclocked sequential networks or a combination of above. We identify the conditions in which the substitution is feasible. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register area minimization also generally leads to faster designs.

Original languageEnglish
Pages (from-to)1583-1587
Number of pages5
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume15
Issue number12
DOIs
Publication statusPublished - 1996 Dec 1

Fingerprint

Computer hardware description languages
Substitution reactions
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

@article{86be3a46957742ec85bca98987e8afad,
title = "Register minimization beyond sharing among variables",
abstract = "Traditionally, it is assumed that every variable in the input HDL (hardware description language) behavioral description needs to be held in a register; a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been shown effective for signal-flow-like computations such as various DSP algorithms. However, the same is not true for the synthesis of controldominated circuits, which usually have variables of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, some unclocked sequential networks or a combination of above. We identify the conditions in which the substitution is feasible. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register area minimization also generally leads to faster designs.",
author = "Tsung-Yi Wu and Lin, {Youn Long}",
year = "1996",
month = "12",
day = "1",
doi = "10.1109/43.552092",
language = "English",
volume = "15",
pages = "1583--1587",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "12",

}

Register minimization beyond sharing among variables. / Wu, Tsung-Yi; Lin, Youn Long.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 12, 01.12.1996, p. 1583-1587.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Register minimization beyond sharing among variables

AU - Wu, Tsung-Yi

AU - Lin, Youn Long

PY - 1996/12/1

Y1 - 1996/12/1

N2 - Traditionally, it is assumed that every variable in the input HDL (hardware description language) behavioral description needs to be held in a register; a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been shown effective for signal-flow-like computations such as various DSP algorithms. However, the same is not true for the synthesis of controldominated circuits, which usually have variables of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, some unclocked sequential networks or a combination of above. We identify the conditions in which the substitution is feasible. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register area minimization also generally leads to faster designs.

AB - Traditionally, it is assumed that every variable in the input HDL (hardware description language) behavioral description needs to be held in a register; a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been shown effective for signal-flow-like computations such as various DSP algorithms. However, the same is not true for the synthesis of controldominated circuits, which usually have variables of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, some unclocked sequential networks or a combination of above. We identify the conditions in which the substitution is feasible. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register area minimization also generally leads to faster designs.

UR - http://www.scopus.com/inward/record.url?scp=0030379796&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030379796&partnerID=8YFLogxK

U2 - 10.1109/43.552092

DO - 10.1109/43.552092

M3 - Article

VL - 15

SP - 1583

EP - 1587

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 12

ER -