Abstract
Traditionally, it is assumed that every variable in the input HDL (hardware description language) behavioral description needs to be held in a register; a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been shown effective for signal-flow-like computations such as various DSP algorithms. However, the same is not true for the synthesis of controldominated circuits, which usually have variables of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, some unclocked sequential networks or a combination of above. We identify the conditions in which the substitution is feasible. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register area minimization also generally leads to faster designs.
Original language | English |
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Pages (from-to) | 1583-1587 |
Number of pages | 5 |
Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Volume | 15 |
Issue number | 12 |
DOIs | |
Publication status | Published - 1996 Dec 1 |
All Science Journal Classification (ASJC) codes
- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering