Abstract
Traditionally, it is assumed that every variable in the input HDL (Hardware Description Language) behavioral description needs to be held in a register; A register can be shared by multiple variables if they have mutually disjoint lifetime intervals. This approach is effective for signal-flow-like computations such as various DSP algorithms. However, it is not the best for the synthesis of control-dominated circuits, which usually have variables/signals of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, or some unclocked sequential networks. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register minimization also leads to both smaller area and faster designs.
| Original language | English |
|---|---|
| Pages (from-to) | 164-169 |
| Number of pages | 6 |
| Journal | Proceedings - Design Automation Conference |
| Publication status | Published - 1995 Jan 1 |
| Event | Proceedings of the 32nd Design Automation Conference - San Francisco, CA, USA Duration: 1995 Jun 12 → 1995 Jun 16 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Control and Systems Engineering
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Register minimization beyond sharing among variables. / Wu, Tsung-Yi; Lin, Youn Long.
In: Proceedings - Design Automation Conference, 01.01.1995, p. 164-169.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - Register minimization beyond sharing among variables
AU - Wu, Tsung-Yi
AU - Lin, Youn Long
PY - 1995/1/1
Y1 - 1995/1/1
N2 - Traditionally, it is assumed that every variable in the input HDL (Hardware Description Language) behavioral description needs to be held in a register; A register can be shared by multiple variables if they have mutually disjoint lifetime intervals. This approach is effective for signal-flow-like computations such as various DSP algorithms. However, it is not the best for the synthesis of control-dominated circuits, which usually have variables/signals of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, or some unclocked sequential networks. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register minimization also leads to both smaller area and faster designs.
AB - Traditionally, it is assumed that every variable in the input HDL (Hardware Description Language) behavioral description needs to be held in a register; A register can be shared by multiple variables if they have mutually disjoint lifetime intervals. This approach is effective for signal-flow-like computations such as various DSP algorithms. However, it is not the best for the synthesis of control-dominated circuits, which usually have variables/signals of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, or some unclocked sequential networks. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register minimization also leads to both smaller area and faster designs.
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M3 - Conference article
AN - SCOPUS:0029226972
SP - 164
EP - 169
JO - Proceedings - Design Automation Conference
JF - Proceedings - Design Automation Conference
SN - 0738-100X
ER -