Register minimization beyond sharing among variables

Tsung Yi Wu, Youn Long Lin

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)


Traditionally, it is assumed that every variable in the input HDL (Hardware Description Language) behavioral description needs to be held in a register; A register can be shared by multiple variables if they have mutually disjoint lifetime intervals. This approach is effective for signal-flow-like computations such as various DSP algorithms. However, it is not the best for the synthesis of control-dominated circuits, which usually have variables/signals of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, or some unclocked sequential networks. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register minimization also leads to both smaller area and faster designs.

Original languageEnglish
Pages (from-to)164-169
Number of pages6
JournalProceedings - Design Automation Conference
Publication statusPublished - 1995 Jan 1
EventProceedings of the 32nd Design Automation Conference - San Francisco, CA, USA
Duration: 1995 Jun 121995 Jun 16

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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