Abstract
NULL Convention Logic (NCL) is a promising design paradigm for constructing low-power robust asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and those registers can account for up to 35% of the overall power consumption of the NCL circuit. This brief presents the Register-Less NCL (RL-NCL) design paradigm, which achieves low power consumption by eliminating pipeline registers, simplifying the control circuit, and supporting fine-grained power gating to mitigate the leakage power of sleeping logic blocks. Compared with the conventional NCL counterpart, the RL-NCL implementation of an 8-bit five-stage pipelined Kogge-Stone adder can reduce power dissipation by 56.4%-72.5% for the input data rate ranging from 10 to 900 MHz. Moreover, the RL-NCL implementation can reduce the transistor count of the adder by 49.5%.
| Original language | English |
|---|---|
| Article number | 7458168 |
| Pages (from-to) | 314-318 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 64 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2017 Mar 1 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Register-Less NULL Convention Logic. / Chang, Meng-Chou; Yang, Po Hung; Pan, Ze Gang.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 3, 7458168, 01.03.2017, p. 314-318.Research output: Contribution to journal › Article
TY - JOUR
T1 - Register-Less NULL Convention Logic
AU - Chang, Meng-Chou
AU - Yang, Po Hung
AU - Pan, Ze Gang
PY - 2017/3/1
Y1 - 2017/3/1
N2 - NULL Convention Logic (NCL) is a promising design paradigm for constructing low-power robust asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and those registers can account for up to 35% of the overall power consumption of the NCL circuit. This brief presents the Register-Less NCL (RL-NCL) design paradigm, which achieves low power consumption by eliminating pipeline registers, simplifying the control circuit, and supporting fine-grained power gating to mitigate the leakage power of sleeping logic blocks. Compared with the conventional NCL counterpart, the RL-NCL implementation of an 8-bit five-stage pipelined Kogge-Stone adder can reduce power dissipation by 56.4%-72.5% for the input data rate ranging from 10 to 900 MHz. Moreover, the RL-NCL implementation can reduce the transistor count of the adder by 49.5%.
AB - NULL Convention Logic (NCL) is a promising design paradigm for constructing low-power robust asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and those registers can account for up to 35% of the overall power consumption of the NCL circuit. This brief presents the Register-Less NCL (RL-NCL) design paradigm, which achieves low power consumption by eliminating pipeline registers, simplifying the control circuit, and supporting fine-grained power gating to mitigate the leakage power of sleeping logic blocks. Compared with the conventional NCL counterpart, the RL-NCL implementation of an 8-bit five-stage pipelined Kogge-Stone adder can reduce power dissipation by 56.4%-72.5% for the input data rate ranging from 10 to 900 MHz. Moreover, the RL-NCL implementation can reduce the transistor count of the adder by 49.5%.
UR - http://www.scopus.com/inward/record.url?scp=85014704214&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85014704214&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2016.2557812
DO - 10.1109/TCSII.2016.2557812
M3 - Article
AN - SCOPUS:85014704214
VL - 64
SP - 314
EP - 318
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-7747
IS - 3
M1 - 7458168
ER -