NULL Convention Logic (NCL) is a promising design paradigm for constructing low-power robust asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and those registers can account for up to 35% of the overall power consumption of the NCL circuit. This brief presents the Register-Less NCL (RL-NCL) design paradigm, which achieves low power consumption by eliminating pipeline registers, simplifying the control circuit, and supporting fine-grained power gating to mitigate the leakage power of sleeping logic blocks. Compared with the conventional NCL counterpart, the RL-NCL implementation of an 8-bit five-stage pipelined Kogge-Stone adder can reduce power dissipation by 56.4%-72.5% for the input data rate ranging from 10 to 900 MHz. Moreover, the RL-NCL implementation can reduce the transistor count of the adder by 49.5%.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2017 Mar|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering