Power-gating current test for static RAM in nanotechnologies

Yuan Wei Chao, Hsin Ling Chen, Chih Jong Chen, Tsung Chu Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 μm technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.

Original languageEnglish
Title of host publication17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
Pages42-45
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Event17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 - Taipei, Taiwan
Duration: 2007 Dec 32007 Dec 5

Other

Other17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
CountryTaiwan
CityTaipei
Period07-12-0307-12-05

All Science Journal Classification (ASJC) codes

  • Media Technology

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  • Cite this

    Chao, Y. W., Chen, H. L., Chen, C. J., & Huang, T. C. (2007). Power-gating current test for static RAM in nanotechnologies. In 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 (pp. 42-45). [4547614] https://doi.org/10.1109/MTDT.2007.4547614