Power-gating current test for static RAM in nanotechnologies

Yuan Wei Chao, Hsin Ling Chen, Chih Jong Chen, Tsung Chu Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 μm technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.

Original languageEnglish
Title of host publication17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
Pages42-45
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Event17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 - Taipei, Taiwan
Duration: 2007 Dec 32007 Dec 5

Other

Other17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
CountryTaiwan
CityTaipei
Period07-12-0307-12-05

Fingerprint

Random access storage
Nanotechnology
Data storage equipment
Threshold voltage
Transistors
Switches

All Science Journal Classification (ASJC) codes

  • Media Technology

Cite this

Chao, Y. W., Chen, H. L., Chen, C. J., & Huang, T. C. (2007). Power-gating current test for static RAM in nanotechnologies. In 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 (pp. 42-45). [4547614] https://doi.org/10.1109/MTDT.2007.4547614
Chao, Yuan Wei ; Chen, Hsin Ling ; Chen, Chih Jong ; Huang, Tsung Chu. / Power-gating current test for static RAM in nanotechnologies. 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007. 2007. pp. 42-45
@inproceedings{b052614748544490aa68cafe0d97f075,
title = "Power-gating current test for static RAM in nanotechnologies",
abstract = "Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 μm technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.",
author = "Chao, {Yuan Wei} and Chen, {Hsin Ling} and Chen, {Chih Jong} and Huang, {Tsung Chu}",
year = "2007",
month = "12",
day = "1",
doi = "10.1109/MTDT.2007.4547614",
language = "English",
isbn = "9781424416561",
pages = "42--45",
booktitle = "17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007",

}

Chao, YW, Chen, HL, Chen, CJ & Huang, TC 2007, Power-gating current test for static RAM in nanotechnologies. in 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007., 4547614, pp. 42-45, 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007, Taipei, Taiwan, 07-12-03. https://doi.org/10.1109/MTDT.2007.4547614

Power-gating current test for static RAM in nanotechnologies. / Chao, Yuan Wei; Chen, Hsin Ling; Chen, Chih Jong; Huang, Tsung Chu.

17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007. 2007. p. 42-45 4547614.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Power-gating current test for static RAM in nanotechnologies

AU - Chao, Yuan Wei

AU - Chen, Hsin Ling

AU - Chen, Chih Jong

AU - Huang, Tsung Chu

PY - 2007/12/1

Y1 - 2007/12/1

N2 - Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 μm technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.

AB - Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 μm technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.

UR - http://www.scopus.com/inward/record.url?scp=50849142848&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50849142848&partnerID=8YFLogxK

U2 - 10.1109/MTDT.2007.4547614

DO - 10.1109/MTDT.2007.4547614

M3 - Conference contribution

AN - SCOPUS:50849142848

SN - 9781424416561

SP - 42

EP - 45

BT - 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007

ER -

Chao YW, Chen HL, Chen CJ, Huang TC. Power-gating current test for static RAM in nanotechnologies. In 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007. 2007. p. 42-45. 4547614 https://doi.org/10.1109/MTDT.2007.4547614