Pipelined VLSI architecture for adaptive image compression

T. Acharya, Po-Yueh Chen, H. Jafarkhani

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In this paper, we present a VLSI architecture for an adaptive image compression system. The architecture exploits the principles of multistage pipelining and underlying data parallelism in order to achieve high throughput and speed. The redundancy of image data is eliminated efficiently by the Discrete Wavelet Transform (DWT). Spectral classification and bit rate allocation methods used in the pipeline makes the encoding system adaptive. The DWT architecture works for both decomposition and reconstruction of images and yields 100% utilization. The basic cell for the DWT architecture has been designed and simulated. Based on the simulation results, the overall system performance is estimated.

Original languageEnglish
Pages (from-to)115-123
Number of pages9
JournalInternational Journal of Robotics and Automation
Volume14
Issue number3
Publication statusPublished - 1999 Dec 1

Fingerprint

VLSI Architecture
Discrete wavelet transforms
Image Compression
Image compression
Wavelet Transform
Data Parallelism
Pipelining
Adaptive systems
High Throughput
Redundancy
System Performance
Encoding
High Speed
Pipelines
Throughput
Decomposition
Decompose
Cell
Architecture
Simulation

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Software
  • Modelling and Simulation
  • Mechanical Engineering
  • Artificial Intelligence
  • Electrical and Electronic Engineering

Cite this

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Pipelined VLSI architecture for adaptive image compression. / Acharya, T.; Chen, Po-Yueh; Jafarkhani, H.

In: International Journal of Robotics and Automation, Vol. 14, No. 3, 01.12.1999, p. 115-123.

Research output: Contribution to journalArticle

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