Pipelined VLSI architecture for adaptive image compression

T. Acharya, Po-Yueh Chen, H. Jafarkhani

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


In this paper, we present a VLSI architecture for an adaptive image compression system. The architecture exploits the principles of multistage pipelining and underlying data parallelism in order to achieve high throughput and speed. The redundancy of image data is eliminated efficiently by the Discrete Wavelet Transform (DWT). Spectral classification and bit rate allocation methods used in the pipeline makes the encoding system adaptive. The DWT architecture works for both decomposition and reconstruction of images and yields 100% utilization. The basic cell for the DWT architecture has been designed and simulated. Based on the simulation results, the overall system performance is estimated.

Original languageEnglish
Pages (from-to)115-123
Number of pages9
JournalInternational Journal of Robotics and Automation
Issue number3
Publication statusPublished - 1999 Dec 1

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Software
  • Modelling and Simulation
  • Mechanical Engineering
  • Artificial Intelligence
  • Electrical and Electronic Engineering

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