Abstract
Sparse matrix-vector multiplication (SpMV) as one of the most significant scientific kernels has been widely used in many scientific disciplines. In practical applications, large-scale spare matrices are usually used for calculation. During these years, Graphic Processing Unit (GPU) has become a powerful platform for high-performance computing, and optimizing SpMV on GPU based systems for efficient performance is the principal interest in many researches. In this paper, we proposed a new method to optimize SpMV on GPUs via index compression. Our index compression method can reduce the index value of the access space. The memory space for recording each column index is significantly reduced from two bytes to one byte, which outperforms the previous work on access performance. The main contributions we make are as follows: (1) Only one byte for each column index is required, which can significantly reduce the working set of the column index and further improve the cache hit ration. (2) Our method can be applied to any kind of matrices, while the previous work can only apply to subset of the matrices. Computational experiments on problems according to the previous work reveal that the best performance improvement ration for ours is up to about 1.5.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of 2018 IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2018 |
| Editors | Bing Xu |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 598-602 |
| Number of pages | 5 |
| ISBN (Electronic) | 9781538645086 |
| DOIs | |
| Publication status | Published - 2018 Dec 14 |
| Event | 3rd IEEE Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2018 - Chongqing, China Duration: 2018 Oct 12 → 2018 Oct 14 |
Publication series
| Name | Proceedings of 2018 IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2018 |
|---|
Other
| Other | 3rd IEEE Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2018 |
|---|---|
| Country | China |
| City | Chongqing |
| Period | 18-10-12 → 18-10-14 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Artificial Intelligence
- Computer Networks and Communications
- Information Systems
- Control and Optimization
- Instrumentation
Cite this
}
Optimizing Sparse Matrix-Vector Multiplication on GPUS via Index Compression. / Sun, Xue; wei, kai-cheng; Lai, Lien-Fu; Tsai, Sung Han; Wu, Chao-Chin.
Proceedings of 2018 IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2018. ed. / Bing Xu. Institute of Electrical and Electronics Engineers Inc., 2018. p. 598-602 8577693 (Proceedings of 2018 IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2018).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Optimizing Sparse Matrix-Vector Multiplication on GPUS via Index Compression
AU - Sun, Xue
AU - wei, kai-cheng
AU - Lai, Lien-Fu
AU - Tsai, Sung Han
AU - Wu, Chao-Chin
PY - 2018/12/14
Y1 - 2018/12/14
N2 - Sparse matrix-vector multiplication (SpMV) as one of the most significant scientific kernels has been widely used in many scientific disciplines. In practical applications, large-scale spare matrices are usually used for calculation. During these years, Graphic Processing Unit (GPU) has become a powerful platform for high-performance computing, and optimizing SpMV on GPU based systems for efficient performance is the principal interest in many researches. In this paper, we proposed a new method to optimize SpMV on GPUs via index compression. Our index compression method can reduce the index value of the access space. The memory space for recording each column index is significantly reduced from two bytes to one byte, which outperforms the previous work on access performance. The main contributions we make are as follows: (1) Only one byte for each column index is required, which can significantly reduce the working set of the column index and further improve the cache hit ration. (2) Our method can be applied to any kind of matrices, while the previous work can only apply to subset of the matrices. Computational experiments on problems according to the previous work reveal that the best performance improvement ration for ours is up to about 1.5.
AB - Sparse matrix-vector multiplication (SpMV) as one of the most significant scientific kernels has been widely used in many scientific disciplines. In practical applications, large-scale spare matrices are usually used for calculation. During these years, Graphic Processing Unit (GPU) has become a powerful platform for high-performance computing, and optimizing SpMV on GPU based systems for efficient performance is the principal interest in many researches. In this paper, we proposed a new method to optimize SpMV on GPUs via index compression. Our index compression method can reduce the index value of the access space. The memory space for recording each column index is significantly reduced from two bytes to one byte, which outperforms the previous work on access performance. The main contributions we make are as follows: (1) Only one byte for each column index is required, which can significantly reduce the working set of the column index and further improve the cache hit ration. (2) Our method can be applied to any kind of matrices, while the previous work can only apply to subset of the matrices. Computational experiments on problems according to the previous work reveal that the best performance improvement ration for ours is up to about 1.5.
UR - http://www.scopus.com/inward/record.url?scp=85060374374&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85060374374&partnerID=8YFLogxK
U2 - 10.1109/IAEAC.2018.8577693
DO - 10.1109/IAEAC.2018.8577693
M3 - Conference contribution
AN - SCOPUS:85060374374
T3 - Proceedings of 2018 IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2018
SP - 598
EP - 602
BT - Proceedings of 2018 IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conference, IAEAC 2018
A2 - Xu, Bing
PB - Institute of Electrical and Electronics Engineers Inc.
ER -