Low test-application time method for EEPLA testing

K. C. Wei, B. D. Liu, J. J. Tang

Research output: Contribution to journalArticle

Abstract

An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected.

Original languageEnglish
Pages (from-to)39-42
Number of pages4
JournalIEE Proceedings: Computers and Digital Techniques
Volume144
Issue number1
DOIs
Publication statusPublished - 1997 Jan 1

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Fingerprint Dive into the research topics of 'Low test-application time method for EEPLA testing'. Together they form a unique fingerprint.

Cite this