Low-power asynchronous NCL pipelines with fine-grain power gating and early sleep

Meng-Chou Chang, Ming Hsun Hsieh, Po Hung Yang

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

null convention logic (NCL) is a promising design paradigm for constructing asynchronous delay-insensitive circuits. This brief presents two novel NCL pipeline structures, called fine-grain power gating NCL with early sleep (FPG-NCL-ES) and fine-grain power gating NCL with early sleep and optimization (FPG-NCL-ES-OPT), which employ both fine-grain power gating and early sleep to achieve lower power consumption. With fine-grain power gating, a logic block in FPG-NCL-ES becomes active only when performing useful work and is power gated to reduce leakage power when inactive. Moreover, with the early sleep mechanism, the multithreshold CMOS (MTCMOS) threshold gates in a pipeline stage can enter the sleep mode early once the data output of this stage has been received by the downstream pipeline stage, without waiting for the next null wavefront to arrive at this stage. Thus, the MTCMOS threshold gates in the FPG-NCL-ES pipeline have a higher probability of staying in the sleep mode than those in the traditional power-gated NCL pipeline. A modified asymmetric C-element is proposed to replace the traditional C-element for supporting early sleep. The FPG-NCL-ES-OPT pipeline employs a circuit simplification to further reduce silicon area and power consumption. Simulation results show that, compared with the traditional NCL counterpart, the FPG-NCL-ES-OPT implementation of the Kogge-Stone adder can achieve a higher maximum sustainable throughput rate, lower power consumption, and lower hardware cost.

Original languageEnglish
Article number6919305
Pages (from-to)957-961
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume61
Issue number12
DOIs
Publication statusPublished - 2014 Dec 1

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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