Low power adders design for portable video terminal

Chien Hung Lin, Shu Chung Yi, Jin Jia Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Many low power CMOS 1-bit full adder cells, formed by transmission gates, have been presented recently. However, the performance of low power adders, directly formed by those 1-bit full adder cells, is not the best. This paper presents a new tapered transmission gate that decreases the propagation delay in the carry chains without increasing power consumption. The design provides an alternative and complementary solution for decreasing the carry propagation delay in low power cell, particularly for those cases where chains of transmission gates are used.

Original languageEnglish
Title of host publicationProceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008
Pages651-654
Number of pages4
DOIs
Publication statusPublished - 2008 Oct 22
Event2008 4th International Conference on Intelligent Information Hiding and Multiedia Signal Processing, IIH-MSP 2008 - Harbin, China
Duration: 2008 Aug 152008 Aug 17

Publication series

NameProceedings - 2008 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IIH-MSP 2008

Other

Other2008 4th International Conference on Intelligent Information Hiding and Multiedia Signal Processing, IIH-MSP 2008
CountryChina
CityHarbin
Period08-08-1508-08-17

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Computer Graphics and Computer-Aided Design
  • Signal Processing

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